DMI-to-JTAG needed to be "sync" to get ack/resp right

[soc.git] / src / soc / config / loadstore.py

diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py
index 37e2bf38f08d18b869fcb4d8295974a00c0df06b..f280227d57d010fccd9fe7d08c335c7c024cecbf 100644 (file)
--- a/src/soc/config/loadstore.py
+++ b/src/soc/config/loadstore.py
@@ -1,20 +1,42 @@
-"""ConfigureableLoadStoreUnit
+"""ConfigureableLoadStoreUnit and ConfigMemoryPortInterface
 
 allows the type of LoadStoreUnit to be run-time selectable
 
+this allows the same code to be used for both small unit tests
+as well as larger ones and so on, without needing large amounts
+of unnecessarily-duplicated code
 """
-from soc.experiment.pimem import TestMemoryLoadStoreUnit
+from soc.experiment.lsmem import TestMemLoadStoreUnit
 from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit
+from soc.experiment.pi2ls import Pi2LSUI
+from soc.experiment.pimem import TestMemoryPortInterface
+from soc.minerva.units.loadstore import BareLoadStoreUnit
 
-
-class ConfigureableLoadStoreUnit:
+class ConfigLoadStoreUnit:
     def __init__(self, pspec):
-        lsidict = {'testmem': TestMemoryLoadStoreUnit,
-                   'test_bare_wb': TestBareLoadStoreUnit,
+        lsidict = {'testmem': TestMemLoadStoreUnit,
+                   'test_bare_wb': TestSRAMBareLoadStoreUnit,
+                   'bare_wb': BareLoadStoreUnit,
                    #'test_cache_wb': TestCacheLoadStoreUnit
                   }
         lsikls = lsidict[pspec.ldst_ifacetype]
-        self.lsi = lsikls(addr_wid=pspec.addr_wid, # address range
+        self.lsi = lsikls(pspec)
+
+
+class ConfigMemoryPortInterface:
+    def __init__(self, pspec):
+        self.pspec = pspec
+        if pspec.ldst_ifacetype == 'testpi':
+            self.pi = TestMemoryPortInterface(addrwid=pspec.addr_wid, # adr bus
+                                              regwid=pspec.reg_wid) # data bus
+            return
+        self.lsmem = ConfigLoadStoreUnit(pspec)
+        self.pi = Pi2LSUI("mem", lsui=self.lsmem.lsi,
+                          addr_wid=pspec.addr_wid, # address range
                           mask_wid=pspec.mask_wid, # cache line range
                           data_wid=pspec.reg_wid)  # data bus width
 
+    def ports(self):
+        if self.pspec.ldst_ifacetype == 'testpi':
+            return self.pi.ports()
+        return list(self.pi.ports()) + self.lsmem.lsi.ports()