first test of down-converted load/store from 64 to 32 bit

[soc.git] / src / soc / config / test / test_fetch.py

diff --git a/src/soc/config/test/test_fetch.py b/src/soc/config/test/test_fetch.py
index 00154dfde5ed2b49e9a32b56db5b02edcc9e05eb..df9caf68871a7100950ec748a5c27b30d4ce3399 100644 (file)
--- a/src/soc/config/test/test_fetch.py
+++ b/src/soc/config/test/test_fetch.py
@@ -7,7 +7,10 @@ from soc.config.ifetch import ConfigFetchUnit
 from collections import namedtuple
 from nmigen.cli import rtlil
 
-from soc.config.test.test_loadstore import TestMemPspec 
+from soc.config.test.test_loadstore import TestMemPspec
+
+import sys
+sys.setrecursionlimit(10**6)
 
 
 def read_from_addr(dut, addr):
@@ -29,14 +32,15 @@ def read_from_addr(dut, addr):
     return res
 
 
-def tst_lsmemtype(ifacetype):
+def tst_lsmemtype(ifacetype, sram_depth=32):
     m = Module()
-    pspec = TestMemPspec(ldst_ifacetype=ifacetype, 
+    pspec = TestMemPspec(ldst_ifacetype=ifacetype,
                          imem_ifacetype=ifacetype, addr_wid=64,
-                                                   mask_wid=4,
-                                                   reg_wid=32)
+                         mask_wid=4,
+                         reg_wid=32,
+                         imem_test_depth=sram_depth)
     dut = ConfigFetchUnit(pspec).fu
-    vl = rtlil.convert(dut, ports=[]) # TODOdut.ports())
+    vl = rtlil.convert(dut, ports=[])  # TODOdut.ports())
     with open("test_fetch_%s.il" % ifacetype, "w") as f:
         f.write(vl)
 
@@ -49,20 +53,21 @@ def tst_lsmemtype(ifacetype):
 
     def process():
 
-        values = [random.randint(0, (1<<32)-1) for x in range(16)]
+        values = [random.randint(0, (1 << 32)-1) for x in range(16)]
         for addr, val in enumerate(values):
             yield mem._array[addr].eq(val)
         yield Settle()
 
         for addr, val in enumerate(values):
             x = yield from read_from_addr(dut, addr << 2)
-            print ("addr, val", addr, hex(val), hex(x))
+            print("addr, val", addr, hex(val), hex(x))
             assert x == val
 
     sim.add_sync_process(process)
     with sim.write_vcd("test_fetch_%s.vcd" % ifacetype, traces=[]):
         sim.run()
 
+
 if __name__ == '__main__':
-    tst_lsmemtype('test_bare_wb')
+    tst_lsmemtype('test_bare_wb', sram_depth=32768)
     tst_lsmemtype('testmem')