Parameterize the issuer on the number of operands and results

[soc.git] / src / soc / consts.py

diff --git a/src/soc/consts.py b/src/soc/consts.py
index f7e55f1a11fe3ec9596b77abaaea2217ef7533a4..25ce875883082f697776e52fade4b4989fa75dcd 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -119,6 +119,8 @@ botchify(MSRb, MSR)
 
 # use this in the simulator
 class PIb:
+    INVALID      = 33    # 1 for an invalid mem err
+    PERMERR      = 35    # 1 for an permanent mem err
     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
     FP           = 43    # 1 if FP exception
     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
@@ -143,6 +145,7 @@ class TT:
     ADDR = 1<<3
     EINT = 1<<4  # external interrupt
     DEC = 1<<5   # decrement counter
-    ILLEG = 1<<6 # currently the max, therefore traptype must be 5 bits
+    MEMEXC = 1<<6 # LD/ST exception
+    ILLEG = 1<<7 # currently the max
     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
-    size = 7 # MUST update this to contain the full number of Trap Types
+    size = 8 # MUST update this to contain the full number of Trap Types