adjust how register copy/setup is done in PowerDecoder2

[soc.git] / src / soc / consts.py

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 561290996a51425b2dac374d2e5df7d538816ee2..25ce875883082f697776e52fade4b4989fa75dcd 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -119,6 +119,8 @@ botchify(MSRb, MSR)
 
 # use this in the simulator
 class PIb:
+    INVALID      = 33    # 1 for an invalid mem err
+    PERMERR      = 35    # 1 for an permanent mem err
     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
     FP           = 43    # 1 if FP exception
     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)