if msb0_end is None:
return r[(field_width - 1) - msb0_start]
else:
- return r[field_slice(msb0_start, msb0_end)]
-
-
-def sel(r, sel_bits, field_width=None):
- """Forms a subfield from a selection of bits of the signal `r`
- ("register").
-
- :param r: signal containing the field from which to select the subfield
- :param sel_bits: bit indices of the subfield, in "MSB 0" convention,
- from most significant to least significant. Note that
- the indices are allowed to be non-contiguous and
- out-of-order.
- :param field_width: field width. If absent, use the signal `r` own width.
- """
- # find the MSB index in LSB0 numbering
- if field_width is None:
- msb = len(r) - 1
- else:
- msb = field_width - 1
- # extract the selected bits
- sig_list = []
- for idx in sel_bits:
- sig_list.append(r[msb - idx])
- # place the LSB at the front of the list,
- # since, in nMigen, Cat starts from the LSB
- sig_list.reverse()
- return Cat(*sig_list)
+ return r[field_slice(msb0_start, msb0_end, field_width)]
# Listed in V3.0B Book III Chap 4.2.1
SPEC_SIZE = 3
-SPEC = SPECb
+SPEC_AUG_SIZE = 2 # augmented subfield size (MSB+LSB above)
+class SPEC:
+ pass
botchify(SPECb, SPEC, SPEC_SIZE-1)
EXTRA2_SIZE = 9
-EXTRA2 = EXTRA2b
+class EXTRA2:
+ pass
botchify(EXTRA2b, EXTRA2, EXTRA2_SIZE-1)
IDX0 = [0, 1, 2]
IDX1 = [3, 4, 5]
IDX2 = [6, 7, 8]
+ MASK = [6, 7, 8]
EXTRA3_SIZE = 9
+
+
+# SVP64 ReMapped Field (from v3.1 EXT001 Prefix)
+class SVP64P:
+ OPC = range(0, 6)
+ SVP64_7_9 = [7, 9]
+ RM = [6, 8] + list(range(10, 32))
+
+# 24 bits in RM
+SVP64P_SIZE = 24
+
+
+# CR SVP64 offsets
+class SVP64CROffs:
+ CR0 = 0 # TODO: increase when CRs are expanded to 128
+ CR1 = 1 # TODO: increase when CRs are expanded to 128
+ CRPred = 4 # TODO: increase when CRs are expanded to 128
+
+
+class SVP64MODEb:
+ # mode bits
+ MOD2_MSB = 0
+ MOD2_LSB = 1
+ # when predicate not set: 0=ignore/skip 1=zero
+ DZ = 3 # for destination
+ SZ = 4 # for source
+ # reduce mode
+ REDUCE = 2 # 0=normal predication 1=reduce mode
+ SVM = 3 # subvector reduce mode 0=independent 1=horizontal
+ CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all
+ # saturation mode
+ N = 2 # saturation signed mode 0=signed 1=unsigned
+ # ffirst and predicate result modes
+ INV = 2 # invert CR sense 0=set 1=unset
+ CR_MSB = 3 # CR bit to update (with Rc=1)
+ CR_LSB = 4
+ RC1 = 4 # update CR as if Rc=1 (when Rc=0)
+ # LD immediate els (element-stride) locations, depending on mode
+ ELS_NORMAL = 2
+ ELS_FFIRST_PRED = 3
+ ELS_SAT = 4
+ # BO bits
+ BO_MSB = 2
+ BO_LSB = 4
+
+
+SVP64MODE_SIZE = 5
+
+
+class SVP64MODE:
+ pass
+
+
+botchify(SVP64MODEb, SVP64MODE, SVP64MODE_SIZE-1)
+
+# add subfields to use with nmutil.sel
+SVP64MODE.MOD2 = [0, 1]
+SVP64MODE.CR = [3, 4]
+
+
+# CR sub-fields
+class CRb:
+ LT = 0
+ GT = 1
+ EQ = 2
+ SO = 3
+
+
+CR_SIZE = 4
+
+
+class CR:
+ pass
+
+
+botchify(CRb, CR, CR_SIZE-1)