CR sub-fields are stored in MSB0 order

[soc.git] / src / soc / consts.py

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 76b16f2b4fd944adc578889aa554a8185e81ebd1..3060c82655b7684c53d05dba2cecf56928527260 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -220,8 +220,8 @@ class SVP64MODEb:
     MOD2_MSB = 0
     MOD2_LSB = 1
     # when predicate not set: 0=ignore/skip 1=zero
-    SZ = 3  # for source
-    DZ = 4  # for destination
+    DZ = 3  # for destination
+    SZ = 4  # for source
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
     SVM = 3  # subvector reduce mode 0=independent 1=horizontal
@@ -237,6 +237,9 @@ class SVP64MODEb:
     ELS_NORMAL = 2
     ELS_FFIRST_PRED = 3
     ELS_SAT = 4
+    # BO bits
+    BO_MSB = 2
+    BO_LSB = 4
 
 
 SVP64MODE_SIZE = 5
@@ -251,3 +254,21 @@ botchify(SVP64MODEb, SVP64MODE, SVP64MODE_SIZE-1)
 # add subfields to use with nmutil.sel
 SVP64MODE.MOD2 = [0, 1]
 SVP64MODE.CR = [3, 4]
+
+
+# CR sub-fields
+class CRb:
+    LT = 0
+    GT = 1
+    EQ = 2
+    SO = 3
+
+
+CR_SIZE = 4
+
+
+class CR:
+    pass
+
+
+botchify(CRb, CR, CR_SIZE-1)