add quick demo/test of reading DMI reg 9

[soc.git] / src / soc / debug / dmi.py

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index bff07d70f569670f752f6dfa63a2fc285f6fd6d7..69bd0be7724830f836f34f6496022cd1bb756b9e 100644 (file)
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -15,14 +15,14 @@ from soc.config.state import CoreState
 
 # DMI register addresses
 class DBGCore:
-    CTRL           = 0b0000
-    STAT           = 0b0001
-    NIA            = 0b0010 # NIA register (read only for now)
-    MSR            = 0b0011 # MSR (read only)
-    GSPR_INDEX     = 0b0100 # GSPR register index
-    GSPR_DATA      = 0b0101 # GSPR register data
-    LOG_ADDR       = 0b0110 # Log buffer address register
-    LOG_DATA       = 0b0111 # Log buffer data register
+    CTRL         = 0b0000
+    STAT         = 0b0001
+    NIA          = 0b0010 # NIA register (read only for now)
+    MSR          = 0b0011 # MSR (read only)
+    GSPR_IDX     = 0b0100 # GSPR register index
+    GSPR_DATA    = 0b0101 # GSPR register data
+    LOG_ADDR     = 0b0110 # Log buffer address register
+    LOG_DATA     = 0b0111 # Log buffer data register
 
 
 # CTRL register (direct actions, write 1 to act, read back 0)
@@ -63,10 +63,10 @@ class DMIInterface(RecordObject):
 class DbgReg(RecordObject):
     def __init__(self, name):
         super().__init__(name=name)
-        self.req_o     = Signal()
-        self.ack_i     = Signal()
-        self.addr_o    = Signal(7) #  includes fast SPRs, others?
-        self.data_i    = Signal(64)
+        self.req     = Signal()
+        self.ack     = Signal()
+        self.addr    = Signal(7) #  includes fast SPRs, others?
+        self.data    = Signal(64)
 
 
 class CoreDebug(Elaboratable):
@@ -115,7 +115,7 @@ class CoreDebug(Elaboratable):
         do_icreset   = Signal()
         terminated   = Signal()
         do_gspr_rd   = Signal()
-        gspr_index   = Signal.like(self.dbg_gpr.addr_o)
+        gspr_index   = Signal.like(self.dbg_gpr.addr)
 
         log_dmi_addr = Signal(32)
         log_dmi_data = Signal(64)
@@ -127,8 +127,8 @@ class CoreDebug(Elaboratable):
 
         # Single cycle register accesses on DMI except for GSPR data
         comb += self.dmi.ack_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA,
-                                      self.dbg_gpr.ack_i, self.dmi.req_i))
-        comb += self.dbg_gpr.req_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA,
+                                      self.dbg_gpr.ack, self.dmi.req_i))
+        comb += self.dbg_gpr.req.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA,
                                       self.dmi.req_i, 0))
 
         # Status register read composition (DBUG_CORE_STAT_xxx)
@@ -145,7 +145,7 @@ class CoreDebug(Elaboratable):
             with m.Case( DBGCore.MSR):
                 comb += self.dmi.dout.eq(self.state.msr)
             with m.Case( DBGCore.GSPR_DATA):
-                comb += self.dmi.dout.eq(self.dbg_gpr.data_i)
+                comb += self.dmi.dout.eq(self.dbg_gpr.data)
             with m.Case( DBGCore.LOG_ADDR):
                 comb += self.dmi.dout.eq(Cat(log_dmi_addr,
                                              self.log_write_addr_o))
@@ -184,7 +184,7 @@ class CoreDebug(Elaboratable):
                         sync += terminated.eq(0)
 
                 # GSPR address
-                with m.Elif(self.dmi.addr_i == DBGCore.GSPR_INDEX):
+                with m.Elif(self.dmi.addr_i == DBGCore.GSPR_IDX):
                     sync += gspr_index.eq(self.dmi.din)
 
                 # Log address
@@ -212,7 +212,7 @@ class CoreDebug(Elaboratable):
             sync += stopping.eq(1)
             sync += terminated.eq(1)
 
-        comb += self.dbg_gpr.addr_o.eq(gspr_index)
+        comb += self.dbg_gpr.addr.eq(gspr_index)
 
         # Core control signals generated by the debug module
         comb += self.core_stop_o.eq(stopping & ~do_step)