add CR read to DMI interface

[soc.git] / src / soc / debug / dmi.py

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index 9c28d2b9f3d804c96e179c08e8c2e24648be04e1..71e493592cd30e8c1298b9434f0308c8ea975353 100644 (file)
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -139,7 +139,7 @@ class CoreDebug(Elaboratable):
         LOG_INDEX_BITS = log2_int(self.LOG_LENGTH)
 
         # Single cycle register accesses on DMI except for GSPR data
-        with m.Switch(.dmi.addr_i):
+        with m.Switch(dmi.addr_i):
             with m.Case(DBGCore.GSPR_DATA):
                 comb += dmi.ack_o.eq(dbg_gpr.ack)
                 comb += dbg_gpr.req.eq(dmi.req_i)