add openocd.cfg experiment

[soc.git] / src / soc / debug / dmi.py

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index 34c45169736827dc3194c6ce5e95fb06be8fff84..39ea799b4da63acddc2081818c2eb0e853327968 100644 (file)
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -52,15 +52,23 @@ class DBGStat:
 
 
 class DMIInterface(RecordObject):
-    def __init__(self, name):
+    def __init__(self, name=None):
         super().__init__(name=name)
         self.addr_i = Signal(4)   # DMI register address
-        self.din    = Signal(64)  # DMI data in (if we=1)
-        self.dout   = Signal(64)  # DMI data out (if we=0)
+        self.din    = Signal(64)  # DMI data write in (if we=1)
+        self.dout   = Signal(64)  # DMI data read out (if we=0)
         self.req_i  = Signal()    # DMI request valid (stb)
         self.we_i   = Signal()    # DMI write-enable
         self.ack_o  = Signal()    # DMI ack request
 
+    def connect_to(self, other):
+        return [self.addr_i.eq(other.addr_i),
+                self.req_i.eq(other.req_i),
+                self.we_i.eq(other.we_i),
+                self.din.eq(other.din),
+                other.ack_o.eq(self.ack_o),
+                other.dout.eq(self.dout),
+                ]
 
 class DbgReg(RecordObject):
     def __init__(self, name):