add openocd.cfg experiment

[soc.git] / src / soc / debug / dmi.py

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index 71e493592cd30e8c1298b9434f0308c8ea975353..39ea799b4da63acddc2081818c2eb0e853327968 100644 (file)
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -24,6 +24,7 @@ class DBGCore:
     LOG_ADDR     = 0b0110 # Log buffer address register
     LOG_DATA     = 0b0111 # Log buffer data register
     CR           = 0b1000 # CR (read only)
+    XER          = 0b1001 # XER (read only) - note this is a TEMPORARY hack
 
 
 # CTRL register (direct actions, write 1 to act, read back 0)
@@ -51,15 +52,23 @@ class DBGStat:
 
 
 class DMIInterface(RecordObject):
-    def __init__(self, name):
+    def __init__(self, name=None):
         super().__init__(name=name)
         self.addr_i = Signal(4)   # DMI register address
-        self.din    = Signal(64)  # DMI data in (if we=1)
-        self.dout   = Signal(64)  # DMI data out (if we=0)
+        self.din    = Signal(64)  # DMI data write in (if we=1)
+        self.dout   = Signal(64)  # DMI data read out (if we=0)
         self.req_i  = Signal()    # DMI request valid (stb)
         self.we_i   = Signal()    # DMI write-enable
         self.ack_o  = Signal()    # DMI ack request
 
+    def connect_to(self, other):
+        return [self.addr_i.eq(other.addr_i),
+                self.req_i.eq(other.req_i),
+                self.we_i.eq(other.we_i),
+                self.din.eq(other.din),
+                other.ack_o.eq(self.ack_o),
+                other.dout.eq(self.dout),
+                ]
 
 class DbgReg(RecordObject):
     def __init__(self, name):
@@ -95,10 +104,13 @@ class CoreDebug(Elaboratable):
         self.state = CoreState("core_dbg")
 
         # GSPR register read port
-        self.dbg_gpr = DbgReg("dbg_gpr")
+        self.d_gpr = DbgReg("d_gpr")
 
         # CR register read port
-        self.dbg_cr = DbgReg("dbg_cr")
+        self.d_cr = DbgReg("d_cr")
+
+        # XER register read port
+        self.d_xer = DbgReg("d_xer")
 
         # Core logging data
         self.log_data_i        = Signal(256)
@@ -113,7 +125,7 @@ class CoreDebug(Elaboratable):
 
         m = Module()
         comb, sync = m.d.comb, m.d.sync
-        dmi, dbg_gpr, dbg_cr = self.dmi, self.dbg_gpr, self.dbg_cr
+        dmi, d_gpr, d_cr, d_xer, = self.dmi, self.d_gpr, self.d_cr, self.d_xer
 
         # DMI needs fixing... make a one clock pulse
         dmi_req_i_1 = Signal()
@@ -128,7 +140,7 @@ class CoreDebug(Elaboratable):
         do_icreset   = Signal()
         terminated   = Signal()
         do_gspr_rd   = Signal()
-        gspr_index   = Signal.like(dbg_gpr.addr)
+        gspr_index   = Signal.like(d_gpr.addr)
 
         log_dmi_addr = Signal(32)
         log_dmi_data = Signal(64)
@@ -141,11 +153,14 @@ class CoreDebug(Elaboratable):
         # Single cycle register accesses on DMI except for GSPR data
         with m.Switch(dmi.addr_i):
             with m.Case(DBGCore.GSPR_DATA):
-                comb += dmi.ack_o.eq(dbg_gpr.ack)
-                comb += dbg_gpr.req.eq(dmi.req_i)
+                comb += dmi.ack_o.eq(d_gpr.ack)
+                comb += d_gpr.req.eq(dmi.req_i)
             with m.Case(DBGCore.CR):
-                comb += dmi.ack_o.eq(dbg_cr.ack)
-                comb += dbg_cr.req.eq(dmi.req_i)
+                comb += dmi.ack_o.eq(d_cr.ack)
+                comb += d_cr.req.eq(dmi.req_i)
+            with m.Case(DBGCore.XER):
+                comb += dmi.ack_o.eq(d_xer.ack)
+                comb += d_xer.req.eq(dmi.req_i)
             with m.Default():
                 comb += dmi.ack_o.eq(dmi.req_i)
 
@@ -163,13 +178,15 @@ class CoreDebug(Elaboratable):
             with m.Case( DBGCore.MSR):
                 comb += dmi.dout.eq(self.state.msr)
             with m.Case( DBGCore.GSPR_DATA):
-                comb += dmi.dout.eq(dbg_gpr.data)
+                comb += dmi.dout.eq(d_gpr.data)
             with m.Case( DBGCore.LOG_ADDR):
                 comb += dmi.dout.eq(Cat(log_dmi_addr, self.log_write_addr_o))
             with m.Case( DBGCore.LOG_DATA):
                 comb += dmi.dout.eq(log_dmi_data)
             with m.Case(DBGCore.CR):
-                comb += dmi.dout.eq(dbg_cr.data)
+                comb += dmi.dout.eq(d_cr.data)
+            with m.Case(DBGCore.XER):
+                comb += dmi.dout.eq(d_xer.data)
 
         # DMI writes
         # Reset the 1-cycle "do" signals
@@ -231,7 +248,7 @@ class CoreDebug(Elaboratable):
             sync += stopping.eq(1)
             sync += terminated.eq(1)
 
-        comb += dbg_gpr.addr.eq(gspr_index)
+        comb += d_gpr.addr.eq(gspr_index)
 
         # Core control signals generated by the debug module
         comb += self.core_stop_o.eq(stopping & ~do_step)
@@ -333,7 +350,9 @@ class CoreDebug(Elaboratable):
         yield self.terminate_i
         yield self.core_stopped_i
         yield from self.state
-        yield from self.dbg_gpr
+        yield from self.d_gpr
+        yield from self.d_cr
+        yield from self.d_xer
         yield self.log_data_i
         yield self.log_read_addr_i
         yield self.log_read_data_o