c4m iopad integration working

[soc.git] / src / soc / debug / jtag.py

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index b83f993e8dc1e60e5fdaa0f56599a6a1b37aa4ce..b1091dac28e31765bdf028191e68bb791894cbed 100644 (file)
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -14,10 +14,10 @@ iotypes = {'-': IOType.In,
            '+': IOType.Out,
            '*': IOType.InTriOut}
 
+# TODO: move to suitable location
+class Pins:
 
-class JTAG(DMITAP):
     def __init__(self):
-        super().__init__(ir_width=4)
 
         # sigh this needs to come from pinmux.
         gpios = []
@@ -25,15 +25,31 @@ class JTAG(DMITAP):
             gpios.append("gpio%d*" % i)
         self.io_names = {'serial': ['tx+', 'rx-'], 'gpio': gpios}
 
+    def __iter__(self):
         # start parsing io_names and create IOConn Records
-        self.ios = []
         for fn, pins in self.io_names.items():
             for pin in pins:
                 # decode the pin name and determine the c4m jtag io type
                 name, pin_type = pin[:-1], pin[-1]
                 iotype = iotypes[pin_type]
                 pin_name = "%s_%s" % (fn, name)
-                self.ios.append(self.add_io(iotype=iotype, name=pin_name))
+                yield (fn, name, iotype, pin_name)
+
+class JTAG(DMITAP, Pins):
+    def __init__(self):
+        DMITAP.__init__(self, ir_width=4)
+        Pins.__init__(self)
+
+        # sigh this needs to come from pinmux.
+        gpios = []
+        for i in range(16):
+            gpios.append("gpio%d*" % i)
+        self.io_names = {'serial': ['tx+', 'rx-'], 'gpio': gpios}
+
+        # start parsing io_names and create IOConn Records
+        self.ios = []
+        for fn, pin, iotype, pin_name in list(self):
+            self.ios.append(self.add_io(iotype=iotype, name=pin_name))
 
         # this is redundant.  or maybe part of testing, i don't know.
         self.sr = self.add_shiftreg(ircode=4, length=3)