update test_dcbz_pi.py test case

[soc.git] / src / soc / debug / jtag.py

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index 45d4ee30f3eb26b52c65faa9e71d74a26cbd2d48..4b4f17a97d672c3f22b668008a1c058ac2500da6 100644 (file)
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -4,7 +4,7 @@ using Staf Verhaegen (Chips4Makers) wishbone TAP
 """
 
 from collections import OrderedDict
-from nmigen import (Module, Signal, Elaboratable)
+from nmigen import (Module, Signal, Elaboratable, Cat)
 from nmigen.cli import rtlil
 from c4m.nmigen.jtag.tap import IOType
 from soc.debug.dmi import  DMIInterface, DBGCore
@@ -13,11 +13,13 @@ from soc.debug.dmi2jtag import DMITAP
 # map from pinmux to c4m jtag iotypes
 iotypes = {'-': IOType.In,
            '+': IOType.Out,
+           '>': IOType.TriOut,
            '*': IOType.InTriOut,
         }
 
 scanlens = {IOType.In: 1,
            IOType.Out: 1,
+           IOType.TriOut: 2,
            IOType.InTriOut: 3,
             }
 
@@ -25,7 +27,7 @@ def dummy_pinset():
     # sigh this needs to come from pinmux.
     gpios = []
     for i in range(16):
-        gpios.append("gpio%d*" % i)
+        gpios.append("%d*" % i)
     return {'uart': ['tx+', 'rx-'],
              'gpio': gpios,
              'i2c': ['sda*', 'scl+']}
@@ -60,32 +62,64 @@ class Pins:
 
 
 class JTAG(DMITAP, Pins):
-    def __init__(self, pinset):
+    # 32-bit data width here so that it matches with litex
+    def __init__(self, pinset, domain, wb_data_wid=32):
+        self.domain = domain
         DMITAP.__init__(self, ir_width=4)
         Pins.__init__(self, pinset)
 
         # enumerate pin specs and create IOConn Records.
         # we store the boundary scan register offset in the IOConn record
         self.ios = [] # these are enumerated in external_ports
+        self.scan_len = 0
         for fn, pin, iotype, pin_name, scan_idx in list(self):
             io = self.add_io(iotype=iotype, name=pin_name)
             io._scan_idx = scan_idx # hmm shouldn't really do this
+            self.scan_len += scan_idx # record full length of boundary scan
             self.ios.append(io)
 
         # this is redundant.  or maybe part of testing, i don't know.
-        self.sr = self.add_shiftreg(ircode=4, length=3)
+        self.sr = self.add_shiftreg(ircode=4, length=3,
+                                    domain=domain)
 
-        # create and connect wishbone 
-        self.wb = self.add_wishbone(ircodes=[5, 6, 7],
-                                   address_width=29, data_width=64,
-                                   name="jtag_wb")
+        # create and connect wishbone
+        self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
+                                   address_width=30, data_width=wb_data_wid,
+                                   granularity=8, # 8-bit wide
+                                   name="jtag_wb",
+                                   domain=domain)
 
         # create DMI2JTAG (goes through to dmi_sim())
-        self.dmi = self.add_dmi(ircodes=[8, 9, 10])
+        self.dmi = self.add_dmi(ircodes=[8, 9, 10],
+                                    domain=domain)
+
+        # use this for enable/disable of parts of the ASIC.
+        # XXX make sure to add the _en sig to en_sigs list
+        self.wb_icache_en = Signal(reset=1)
+        self.wb_dcache_en = Signal(reset=1)
+        self.wb_sram_en = Signal(reset=1)
+        self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
+                                     self.wb_sram_en)
+        self.sr_en = self.add_shiftreg(ircode=11, length=len(en_sigs),
+                                       domain=domain)
 
     def elaborate(self, platform):
         m = super().elaborate(platform)
         m.d.comb += self.sr.i.eq(self.sr.o) # loopback as part of test?
+
+        # provide way to enable/disable wishbone caches and SRAM
+        # just in case of issues
+        # see https://bugs.libre-soc.org/show_bug.cgi?id=520
+        with m.If(self.sr_en.oe):
+            m.d.sync += self.en_sigs.eq(self.sr_en.o)
+        # also make it possible to read the enable/disable current state
+        with m.If(self.sr_en.ie):
+            m.d.comb += self.sr_en.i.eq(self.en_sigs)
+
+        # create a fake "stall"
+        #wb = self.wb
+        #m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support
+
         return m
 
     def external_ports(self):