update test_dcbz_pi.py test case

[soc.git] / src / soc / debug / jtag.py

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index 5cac2cd44c8868efbaa0ac4e0148a9f6a5d11be2..4b4f17a97d672c3f22b668008a1c058ac2500da6 100644 (file)
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -62,7 +62,9 @@ class Pins:
 
 
 class JTAG(DMITAP, Pins):
-    def __init__(self, pinset, wb_data_wid=64):
+    # 32-bit data width here so that it matches with litex
+    def __init__(self, pinset, domain, wb_data_wid=32):
+        self.domain = domain
         DMITAP.__init__(self, ir_width=4)
         Pins.__init__(self, pinset)
 
@@ -77,22 +79,29 @@ class JTAG(DMITAP, Pins):
             self.ios.append(io)
 
         # this is redundant.  or maybe part of testing, i don't know.
-        self.sr = self.add_shiftreg(ircode=4, length=3)
+        self.sr = self.add_shiftreg(ircode=4, length=3,
+                                    domain=domain)
 
         # create and connect wishbone
         self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
-                                   address_width=29, data_width=wb_data_wid,
-                                   name="jtag_wb")
+                                   address_width=30, data_width=wb_data_wid,
+                                   granularity=8, # 8-bit wide
+                                   name="jtag_wb",
+                                   domain=domain)
 
         # create DMI2JTAG (goes through to dmi_sim())
-        self.dmi = self.add_dmi(ircodes=[8, 9, 10])
+        self.dmi = self.add_dmi(ircodes=[8, 9, 10],
+                                    domain=domain)
 
         # use this for enable/disable of parts of the ASIC.
-        # NOTE: increase length parameter when adding new enable signals
-        self.sr_en = self.add_shiftreg(ircode=11, length=3)
+        # XXX make sure to add the _en sig to en_sigs list
         self.wb_icache_en = Signal(reset=1)
         self.wb_dcache_en = Signal(reset=1)
         self.wb_sram_en = Signal(reset=1)
+        self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
+                                     self.wb_sram_en)
+        self.sr_en = self.add_shiftreg(ircode=11, length=len(en_sigs),
+                                       domain=domain)
 
     def elaborate(self, platform):
         m = super().elaborate(platform)
@@ -101,13 +110,15 @@ class JTAG(DMITAP, Pins):
         # provide way to enable/disable wishbone caches and SRAM
         # just in case of issues
         # see https://bugs.libre-soc.org/show_bug.cgi?id=520
-        en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
-                      self.wb_sram_en)
         with m.If(self.sr_en.oe):
-            m.d.sync += en_sigs.eq(self.sr_en.o)
+            m.d.sync += self.en_sigs.eq(self.sr_en.o)
         # also make it possible to read the enable/disable current state
         with m.If(self.sr_en.ie):
-            m.d.comb += self.sr_en.i.eq(en_sigs)
+            m.d.comb += self.sr_en.i.eq(self.en_sigs)
+
+        # create a fake "stall"
+        #wb = self.wb
+        #m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support
 
         return m