update test_dcbz_pi.py test case

[soc.git] / src / soc / debug / jtagutils.py

diff --git a/src/soc/debug/jtagutils.py b/src/soc/debug/jtagutils.py
index f0b1830d23cfe4c4f5ae762191cc5b653e29ddd2..a642bd1f358cbab7f639505a3f5475ec0625ae7c 100644 (file)
--- a/src/soc/debug/jtagutils.py
+++ b/src/soc/debug/jtagutils.py
@@ -22,9 +22,10 @@ def client_sync(dut):
 
 def tms_state_set(dut, bits):
     for bit in bits:
-        yield dut.cbus.tck.eq(1)
         yield dut.cbus.tms.eq(bit)
         yield from client_sync(dut)
+        yield dut.cbus.tck.eq(1)
+        yield from client_sync(dut)
         yield
         yield dut.cbus.tck.eq(0)
         yield from client_sync(dut)
@@ -71,17 +72,24 @@ def jtag_set_idle(dut):
     yield from tms_state_set(dut, [1, 1, 0])
 
 
-def jtag_read_write_reg(dut, addr, d_len, d_in=0):
+def jtag_set_ir(dut, addr):
     yield from jtag_set_run(dut)
     yield from jtag_set_shift_ir(dut)
-    yield from tms_data_getset(dut, 0, dut._ir_width, addr)
+    result = yield from tms_data_getset(dut, 0, dut._ir_width, addr)
     yield from jtag_set_idle(dut)
+    return result
+
 
+def jtag_set_get_dr(dut, d_len, d_in=0):
     yield from jtag_set_shift_dr(dut)
     result = yield from tms_data_getset(dut, 0, d_len, d_in)
     yield from jtag_set_idle(dut)
     return result
 
+def jtag_read_write_reg(dut, addr, d_len, d_in=0):
+    yield from jtag_set_ir(dut, addr)
+    return (yield from jtag_set_get_dr(dut, d_len, d_in))
+
 
 def jtag_srv(dut):
     while not dut.stop: