decoder immediate b split out to DecodeBImm

[soc.git] / src / soc / decoder / decode2execute1.py

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index 410cb7eca0b003afad8a9d8775fa1e27c100a8eb..98ed32f67790453cefb03a0f793fd539d6514bcb 100644 (file)
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -6,6 +6,7 @@ based on Anton Blanchard microwatt decode2.vhdl
 from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject
 from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
+from soc.consts import TT
 
 
 class Data(Record):
@@ -41,7 +42,7 @@ class Decode2ToOperand(RecordObject):
         self.lk = Signal(reset_less=True)
         self.rc = Data(1, "rc")
         self.oe = Data(1, "oe")
-        self.invert_a = Signal(reset_less=True)
+        self.invert_in = Signal(reset_less=True)
         self.zero_a = Signal(reset_less=True)
         self.input_carry = Signal(CryIn, reset_less=True)
         self.output_carry = Signal(reset_less=True)
@@ -54,10 +55,10 @@ class Decode2ToOperand(RecordObject):
         self.byte_reverse  = Signal(reset_less=True)
         self.sign_extend  = Signal(reset_less=True)# do we need this?
         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
-        self.traptype  = Signal(5, reset_less=True) # see trap main_stage.py
+        self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
         self.trapaddr  = Signal(13, reset_less=True)
-        self.read_cr_whole = Signal(reset_less=True)
-        self.write_cr_whole = Signal(reset_less=True)
+        self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
+        self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
         self.write_cr0 = Signal(reset_less=True)
 
 
@@ -78,7 +79,7 @@ class Decode2ToExecute1Type(RecordObject):
         self.read_spr1 = Data(SPR, name="spr1")
         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 
-        self.xer_in = Signal(reset_less=True)   # xer might be read
+        self.xer_in = Signal(3, reset_less=True)   # xer might be read
         self.xer_out = Signal(reset_less=True)  # xer might be written
 
         self.read_fast1 = Data(3, name="fast1")