use copy of FHDLTestCase

[soc.git] / src / soc / decoder / formal / proof_decoder.py

diff --git a/src/soc/decoder/formal/proof_decoder.py b/src/soc/decoder/formal/proof_decoder.py
index 6aa1bc145db5f8f667b7ddffa10777b8830358a5..e1d793eafbe083c9a1b98ccc656d897926329c4b 100644 (file)
--- a/src/soc/decoder/formal/proof_decoder.py
+++ b/src/soc/decoder/formal/proof_decoder.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal, Elaboratable, Cat
 from nmigen.asserts import Assert, AnyConst, Assume
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 
 from soc.decoder.power_decoder import create_pdecode, PowerOp
 from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,