## Shift address bits 61--12 right by 0--47 bits and
## supply the least significant 16 bits of the result.
def addrshift(addr,shift):
- # shift : unsigned(5 downto 0);
- print("addrshift")
- print("addr",addr)
-
- sh1 = None # std_ulogic_vector(30 downto 0);
- sh2 = None # std_ulogic_vector(18 downto 0);
- result = None # std_ulogic_vector(15 downto 0);
-
- n = 64
- if shift[0:1].value==0:
- print("s1==0")
- sh1 = addr[n-42-1:n-12] # r.addr(42 downto 12);
- elif shift[0:1].value==1:
- print("s1==1")
- sh1 = addr[n-58-1:n-28] # r.addr(58 downto 28);
- else:
- print("s1==else")
- zero = SelectableInt(0,13) # "0000000000000"
- sh1 = selectconcat(zero,addr[n-61-1:n-44]) # r.addr(61 downto 44);
- print("sh1=",sh1)
-
- n=31
- assert(sh1.bits==n)
-
- if shift[1:2].value==0:
- print("s2==0")
- sh2 = sh1[n-18-1:n] # sh1(18 downto 0);
- elif shift[1:2].value==1:
- print("s2==2")
- sh2 = sh1[n-22-1:n-4] # sh1(22 downto 4);
- elif shift[1:2].value==2:
- print("s2==3")
- sh2 = sh1[n-26-1:n-8] # sh1(26 downto 8);
- else:
- print("s2==else")
- sh2 = sh1[n-30-1:n-12] # sh1(30 downto 12);
- print("sh2=",sh2)
-
- n=19
- assert(sh2.bits==n)
-
- if shift[3:4].value==0:
- print("s3==0")
- result = sh2[n-15-1:n] # sh2(15 downto 0);
- print("xxx",result)
- elif shift[3:4].value==1:
- print("s3==2")
- result = sh2[n-16-1:n-1] # sh2(16 downto 1);
- elif shift[3:4].value==2:
- print("s3==3")
- result = sh2[n-17-1:n-2] # sh2(17 downto 2);
- else:
- print("s3==else")
- result = sh2[n-18-1:n-3] # sh2(18 downto 3);
-
- print("result of addrshift",result)
-
- n=16
- assert(result.bits==n)
-
- return result
+ x = addr.value >> shift.value
+ return SelectableInt(x,16)
def NLB(x):
"""
"""
-testaddr = 0x10000
testmem = {
0x10000: # PARTITION_TABLE_2 (not implemented yet)
0x30000: # RADIX_ROOT_PTE
# V = 1 L = 0 NLB = 0x400 NLS = 9
0x8000000000040009,
-######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
0x40000: # RADIX_SECOND_LEVEL
# V = 1 L = 1 SW = 0 RPN = 0
# R = 1 C = 1 ATT = 0 EAA 0x7
# RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
0x40000000000300ad,
}
-
+# this one has a 2nd level RADIX with a RPN of 0x5000
+testmem2 = {
+
+ 0x10000: # PARTITION_TABLE_2 (not implemented yet)
+ # PATB_GR=1 PRTB=0x1000 PRTS=0xb
+ 0x800000000100000b,
+
+ 0x30000: # RADIX_ROOT_PTE
+ # V = 1 L = 0 NLB = 0x400 NLS = 9
+ 0x8000000000040009,
+ 0x40000: # RADIX_SECOND_LEVEL
+ # V = 1 L = 1 SW = 0 RPN = 0x5000
+ # R = 1 C = 1 ATT = 0 EAA 0x7
+ 0xc000000005000187,
+
+ 0x1000000: # PROCESS_TABLE_3
+ # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
+ 0x40000000000300ad,
+ }
+
+
+testresult = """
+ prtbl = 1000000
+ DCACHE GET 1000000 PROCESS_TABLE_3
+ DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
+ DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
+ DCACHE GET 10000 PARTITION_TABLE_2
+translated done 1 err 0 badtree 0 addr 40000 pte 0
+"""
# see qemu/target/ppc/mmu-radix64.c for reference
class RADIX:
#shift = SelectableInt(0, 32)
pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
- # use pte to caclculate phys address
- return self.mem.ld(address, width, swap, check_in_mem)
+
+ # use pte to load from phys address
+ return self.mem.ld(pte.value, width, swap, check_in_mem)
# XXX set SPRs on error
(shift, mbits, pgbase) = self._decode_prte(addr)
pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
- # use pte to caclculate phys address (addr)
- return self.mem.st(addr.value, v, width, swap)
+ # use pte to store at phys address
+ return self.mem.st(pte.value, v, width, swap)
# XXX set SPRs on error
def _next_level(self, addr, entry_width, swap, check_in_mem):
# implement read access to mmu mem here
- value = 0
- if addr.value in testmem:
- value = testmem[addr.value]
- else:
- print("not found")
+ # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
+ value = self.mem.ld(addr.value, 8, False, check_in_mem)
+ assert(value is not None, "address lookup %x not found" % addr.value)
- ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
print("addr", hex(addr.value))
data = SelectableInt(value, 64) # convert to SelectableInt
print("value", hex(value))
print
# get address of root entry
+ shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
+ print("starting with prtable, addr_next",addr_next)
+
+ assert(addr_next.bits == 64)
+ assert(addr_next.value == 0x1000000) #TODO
+
+ # read an entry from prtable
+ swap = False
+ check_in_mem = False
+ entry_width = 8
+ data = self._next_level(addr_next, entry_width, swap, check_in_mem)
+ print("pr_table",data)
+
+ # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
+ shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
+ assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
+ print("shift",shift)
+
+ # mbits := unsigned('0' & data(4 downto 0));
+ mbits = selectconcat(SelectableInt(0,1), data[58:63])
+ assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
+ print("mbits",mbits)
+
+ new_shift = self._segment_check(addr, mbits, shift)
+ print("new_shift",new_shift)
addr_next = SelectableInt(0x30000,64) # radix root for testing
+ # this needs to be calculated using the code above
# walk tree starts on prtbl
while True:
if not valid:
return "invalid" # TODO: return error
if leaf:
+ print ("is leaf, checking perms")
ok = self._check_perms(data, priv, mode)
if ok == True: # data was ok, found phys address, return it?
- return addr_next
+ paddr = self._get_pte(addrsh, addr, data)
+ print (" phys addr", hex(paddr.value))
+ return paddr
return ok # return the error code
else:
newlookup = self._new_lookup(data, mbits, shift)
print(mask) #SelectableInt(value=0x9, bits=4)
print(pgbase) #SelectableInt(value=0x40000, bits=56)
print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
- pgbase = SelectableInt(pgbase.value,64)
+ pgbase = SelectableInt(pgbase.value, 64)
addrsh = addrshift(addr,shift)
addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
print("addr_next",addr_next)
print("addrsh",addrsh)
- assert(addr_next == 0x40000)
- return "TODO verify next level"
def _new_lookup(self, data, mbits, shift):
"""
# below *directly* match the spec, unlike microwatt which
# has to turn them around (to LE)
mask = genmask(shift, 44)
- nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
+ nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
print ("RADIX _segment_check nonzero", bin(nonzero.value))
print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
- if addr[0] != addr[1] or nonzero == 1:
+ if addr[0] != addr[1] or nonzero != 0:
return "segerror"
limit = shift + (31 - 12)
if mbits < 5 or mbits > 16 or mbits > limit:
- return "badtree"
+ return "badtree mbits="+str(mbits)+" limit="+str(limit)
new_shift = shift + (31 - 12) - mbits
return new_shift
(effpid(31 downto 8) and finalmask(23 downto 0))) &
effpid(7 downto 0) & "0000";
"""
- print ("_get_prtable_addr_", shift, prtbl, addr, pid)
+ print ("_get_prtable_addr", shift, prtbl, addr, pid)
finalmask = genmask(shift, 44)
finalmask24 = finalmask[20:44]
if addr[0].value == 1:
effpid = SelectableInt(0, 32)
else:
effpid = pid #self.pid # TODO, check on this
- zero16 = SelectableInt(0, 16)
+ zero8 = SelectableInt(0, 8)
zero4 = SelectableInt(0, 4)
- res = selectconcat(zero16,
+ res = selectconcat(zero8,
prtbl[8:28], #
(prtbl[28:52] & ~finalmask24) | #
(effpid[0:24] & finalmask24), #
(r.addr(55 downto 12) and finalmask))
& r.pde(11 downto 0);
"""
+ shift.value = 12
finalmask = genmask(shift, 44)
zero8 = SelectableInt(0, 8)
+ rpn = pde[8:52] # RPN = Real Page Number
+ abits = addr[8:52] # non-masked address bits
+ print(" get_pte RPN", hex(rpn.value))
+ print(" abits", hex(abits.value))
+ print(" shift", shift.value)
+ print(" finalmask", bin(finalmask.value))
res = selectconcat(zero8,
- (pde[8:52] & ~finalmask) | #
- (addr[8:52] & finalmask), #
- pde[52:64],
+ (rpn & ~finalmask) | #
+ (abits & finalmask), #
+ addr[52:64],
)
return res
-
class TestRadixMMU(unittest.TestCase):
def test_genmask(self):
mask = genmask(shift, 43)
print (" mask", bin(mask.value))
- self.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
+ self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
def test_get_pgtable_addr(self):
pgbase = SelectableInt(0,64)
addrsh = SelectableInt(0,16)
ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
- print("ret=",ret)
- assert(ret==0)
+ print("ret=", ret)
+ self.assertEqual(ret, 0, "pgtbl_addr should be 0")
+
+ def test_walk_tree_1(self):
+
+ # test address as in
+ # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
+ testaddr = 0x1000
+ expected = 0x1000
+
+ # starting prtbl
+ prtbl = 0x1000000
+
+ # set up dummy minimal ISACaller
+ spr = {'DSISR': SelectableInt(0, 64),
+ 'DAR': SelectableInt(0, 64),
+ 'PIDR': SelectableInt(0, 64),
+ 'PRTBL': SelectableInt(prtbl, 64)
+ }
+ # set problem state == 0 (other unit tests, set to 1)
+ msr = SelectableInt(0, 64)
+ msr[MSRb.PR] = 0
+ class ISACaller: pass
+ caller = ISACaller()
+ caller.spr = spr
+ caller.msr = msr
+
+ shift = SelectableInt(5, 6)
+ mask = genmask(shift, 43)
+ print (" mask", bin(mask.value))
+
+ mem = Mem(row_bytes=8, initial_mem=testmem)
+ mem = RADIX(mem, caller)
+ # -----------------------------------------------
+ # |/|RTS1|/| RPDB | RTS2 | RPDS |
+ # -----------------------------------------------
+ # |0|1 2|3|4 55|56 58|59 63|
+ data = SelectableInt(0, 64)
+ data[1:3] = 0b01
+ data[56:59] = 0b11
+ data[59:64] = 0b01101 # mask
+ data[55] = 1
+ (rts, mbits, pgbase) = mem._decode_prte(data)
+ print (" rts", bin(rts.value), rts.bits)
+ print (" mbits", bin(mbits.value), mbits.bits)
+ print (" pgbase", hex(pgbase.value), pgbase.bits)
+ addr = SelectableInt(0x1000, 64)
+ check = mem._segment_check(addr, mbits, shift)
+ print (" segment check", check)
+
+ print("walking tree")
+ addr = SelectableInt(testaddr,64)
+ # pgbase = None
+ mode = None
+ #mbits = None
+ shift = rts
+ result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
+ print(" walking tree result", result)
+ print("should be", testresult)
+ self.assertEqual(result.value, expected,
+ "expected 0x%x got 0x%x" % (expected,
+ result.value))
+
+
+ def test_walk_tree_2(self):
+
+ # test address slightly different
+ testaddr = 0x1101
+ expected = 0x5001101
+
+ # starting prtbl
+ prtbl = 0x1000000
- def test_walk_tree(self):
# set up dummy minimal ISACaller
spr = {'DSISR': SelectableInt(0, 64),
'DAR': SelectableInt(0, 64),
'PIDR': SelectableInt(0, 64),
- 'PRTBL': SelectableInt(0, 64)
+ 'PRTBL': SelectableInt(prtbl, 64)
}
# set problem state == 0 (other unit tests, set to 1)
msr = SelectableInt(0, 64)
mask = genmask(shift, 43)
print (" mask", bin(mask.value))
- mem = Mem(row_bytes=8)
+ mem = Mem(row_bytes=8, initial_mem=testmem2)
mem = RADIX(mem, caller)
# -----------------------------------------------
# |/|RTS1|/| RPDB | RTS2 | RPDS |
shift = rts
result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
print(" walking tree result", result)
+ print("should be", testresult)
+ self.assertEqual(result.value, expected,
+ "expected 0x%x got 0x%x" % (expected,
+ result.value))
if __name__ == '__main__':
projects / soc.git / blobdiff