Fix bug with ROTL32 helper

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index a0381b9de6f919e67de8340d4c265194af3217b4..239e1d462c7c164ffc9f7393a4ab710271968438 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -211,16 +211,16 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[1] = -1
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
-            self.assertEqual(sim.gpr(3), SelectableInt(0xfe000fff, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0xfffffffffe000fff, 64))
 
     def test_rlwimi(self):
         lst = ["rlwimi 3, 1, 5, 20, 6"]
         initial_regs = [0] * 32
-        initial_regs[1] = 0xdeadbeef
+        initial_regs[1] = 0xffffffffdeadbeef
         initial_regs[3] = 0x12345678
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
-            self.assertEqual(sim.gpr(3), SelectableInt(0xd4345dfb, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64))
 
     def test_mtcrf(self):
         for i in range(4):