Add shift test to test_caller, fix fixedshift being weird on 32 bit shifts

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 15a8997ed2e435580f4c7e7e3aa1108c50e74f0f..467d6d210c6a38d5585284303ce56ba384349f2a 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -154,7 +154,19 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program)
             # Verified with qemu
             self.assertEqual(sim.gpr(2), SelectableInt(0x37, 64))
-                    
+
+    def test_branch_loop_ctr(self):
+        lst = ["addi 1, 0, 0",
+               "addi 2, 0, 7",
+               "mtspr 9, 2",    # set ctr to 7
+               "addi 1, 1, 5",
+               "bc 16, 0, -0x4"]  # bdnz to the addi above
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            # Verified with qemu
+            self.assertEqual(sim.gpr(1), SelectableInt(0x23, 64))
+
+
 
     def test_add_compare(self):
         lst = ["addis 1, 0, 0xffff",
@@ -175,6 +187,15 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program)
             self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
 
+    def test_shift(self):
+        lst = ["slw 1, 3, 2"]
+        initial_regs = [0] * 32
+        initial_regs[3] = 0xdeadbeefcafebabe
+        initial_regs[2] = 5
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 32))
+
     def test_mtcrf(self):
         for i in range(4):
             # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for