pdecode = create_pdecode()
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- simulator = ISA(pdecode2, initial_regs, initial_sprs)
+ simulator = ISA(pdecode2, initial_regs, initial_sprs, 0)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
gen = generator.generate_instructions()
print(sim.gpr(1))
self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+ @unittest.skip("broken")
def test_addpcis(self):
lst = ["addpcis 1, 0x1",
"addpcis 2, 0x1",