add RADIX skeleton and unit test

[soc.git] / src / soc / decoder / isa / test_caller_radix.py

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
new file mode 100644 (file)
index 0000000..5292850
--- /dev/null
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -0,0 +1,17 @@
+from nmigen import Module, Signal
+#from nmigen.back.pysim import Simulator, Delay, Settle
+from nmutil.formaltest import FHDLTestCase
+#import unittest
+from soc.decoder.isa.caller import ISACaller
+from soc.decoder.power_decoder import (create_pdecode)
+from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.simulator.program import Program
+from soc.decoder.isa.caller import ISACaller, inject, RADIX
+from soc.decoder.selectable_int import SelectableInt
+from soc.decoder.orderedset import OrderedSet
+from soc.decoder.isa.all import ISA
+
+if __name__ == "__main__":
+    radix = RADIX(None,None) #first test to avoid syntax errors
+    radix._walk_tree()
+    print("DONE")