update test case for radix mmu

[soc.git] / src / soc / decoder / isa / test_caller_radix.py

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index a892e4c1631995200905186d127ce196867ea211..cec96b667a9ada6f6507403b60ecc61f226becfb 100644 (file)
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -12,6 +12,24 @@ from soc.decoder.orderedset import OrderedSet
 from soc.decoder.isa.all import ISA
 from soc.decoder.isa.test_caller import run_tst
 
+testmem = {
+
+           0x10000:    # PARTITION_TABLE_2 (not implemented yet)
+                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
+           0x800000000100000b,
+
+           0x30000:     # RADIX_ROOT_PTE
+                        # V = 1 L = 0 NLB = 0x400 NLS = 9
+           0x8000000000040009,
+           0x40000:     # RADIX_SECOND_LEVEL
+                        # V = 1 L = 1 SW = 0 RPN = 0
+                        # R = 1 C = 1 ATT = 0 EAA 0x7
+           0xc000000000000187,
+
+           0x1000000:   # PROCESS_TABLE_3
+                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
+           0x40000000000300ad,
+          }
 
 class DecoderTestCase(FHDLTestCase):
 
@@ -26,7 +44,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
-        simulator = run_tst(prog, initial_regs,mmu=True)
+        simulator = run_tst(prog, initial_regs,mmu=True,mem=testmem)
         simulator.gpr.dump()
         return simulator