"addi 2, 0, 0x0008",
"addi 5, 0, 0x1234",
"addi 6, 0, 0x1235",
- "svstw 5.v, 0(1.v)",
- "svlwz 9.v, 0(1.v)"])
+ "sv.stw 5.v, 0(1.v)",
+ "sv.lwz 9.v, 0(1.v)"])
lst = list(lst)
# SVSTATE (in this case, VL=2)
# - dests are 5 and 6
# - source mask says "pick first element from source (5)
# - dest mask says "pick *second* element from dest (10)
+ #
# therefore the operation that's carried out is:
# GPR(10) = extsb(GPR(5))
- # this is a type of back-to-back VGATHER and VSCATTER but it applies
+ #
+ # this is a type of back-to-back VREDUCE and VEXPAND but it applies
# to *operations*, not just MVs like in traditional Vector ISAs
+ # ascii graphic:
+ #
+ # reg num 0 1 2 3 4 5 6 7 8 9 10
+ # src ~r3=0b01 Y N
+ # |
+ # +-----+
+ # |
+ # dest r3=0b10 N Y
- isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v'
+ isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
# initial values in GPR regfile
initial_regs = [0] * 32
initial_regs[3] = 0b10 # predicate mask
- initial_regs[9] = 0x91
- initial_regs[10] = 0x90
+ initial_regs[9] = 0x91 # source ~r3 is 0b01 so this will be used
+ initial_regs[10] = 0x90 # this gets skipped
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
svstate.vl[0:7] = 2 # VL
print ("SVSTATE", bin(svstate.spr.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
- expected_regs[5] = 0x0
- expected_regs[6] = 0xffff_ffff_ffff_ff91
+ expected_regs[5] = 0x0 # dest r3 is 0b10: skip
+ expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, initial_regs, svstate)
self._check_regs(sim, expected_regs)
- def tst_sv_add_intpred(self):
+ def test_sv_extsw_intpred_dz(self):
+ # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
+ isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
+ ])
+ lst = list(isa)
+ print ("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[3] = 0b01 # predicate mask (dest)
+ initial_regs[5] = 0xfeed # going to be overwritten
+ initial_regs[6] = 0xbeef # going to be overwritten (with zero)
+ initial_regs[9] = 0x91 # dest r3 is 0b01 so this will be used
+ initial_regs[10] = 0x90 # this gets read but the output gets zero'd
+ # SVSTATE (in this case, VL=2)
+ svstate = SVP64State()
+ svstate.vl[0:7] = 2 # VL
+ svstate.maxvl[0:7] = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.spr.asint()))
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
+ expected_regs[6] = 0 # 2nd bit of r3 is 1: zero
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate)
+ self._check_regs(sim, expected_regs)
+
+ def test_sv_add_intpred(self):
# adds, integer predicated mask r3=0b10
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
sim = self.run_tst_program(program, initial_regs, svstate)
self._check_regs(sim, expected_regs)
- def tst_sv_add_cr_pred(self):
+ def test_sv_add_cr_pred(self):
# adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# r1 is scalar so ENDS EARLY
- isa = SVP64Asm(['svadd 1, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
- isa = SVP64Asm(['svadd 1.v, 5, 9.v'
+ isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
])
lst = list(isa)
print ("listing", lst)
def tst_sv_add_vl_0(self):
# adds:
# none because VL is zer0
- isa = SVP64Asm(['svadd 1, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
# adds when Rc=1: TODO CRs higher up
# 1 = 5 + 9 => 0 = -1+1 CR0=0b100
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
- isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
self.assertEqual(CR0, SelectableInt(2, 4))
self.assertEqual(CR1, SelectableInt(4, 4))
+ def test_intpred_vcompress(self):
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11
+ # src r3=0b101 Y N Y
+ # | |
+ # +-------+ |
+ # | +-----------+
+ # | |
+ # dest always Y Y Y
+
+ isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
+ lst = list(isa)
+ print("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[3] = 0b101 # predicate mask
+ initial_regs[9] = 0x90 # source r3 is 0b101 so this will be used
+ initial_regs[10] = 0x91 # this gets skipped
+ initial_regs[11] = 0x92 # source r3 is 0b101 so this will be used
+ # SVSTATE (in this case, VL=3)
+ svstate = SVP64State()
+ svstate.vl[0:7] = 3 # VL
+ svstate.maxvl[0:7] = 3 # MAXVL
+ print("SVSTATE", bin(svstate.spr.asint()))
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ expected_regs[5] = 0xffff_ffff_ffff_ff90 # (from r9)
+ expected_regs[6] = 0xffff_ffff_ffff_ff92 # (from r11)
+ expected_regs[7] = 0x0 # (VL loop runs out before we can use it)
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate)
+ self._check_regs(sim, expected_regs)
+
+ def test_intpred_vexpand(self):
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11
+ # src always Y Y Y
+ # | |
+ # +-------+ |
+ # | +------+
+ # | |
+ # dest r3=0b101 Y N Y
+
+ isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v'])
+ lst = list(isa)
+ print("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[3] = 0b101 # predicate mask
+ initial_regs[9] = 0x90 # source is "always", so this will be used
+ initial_regs[10] = 0x91 # likewise
+ initial_regs[11] = 0x92 # the VL loop runs out before we can use it
+ # SVSTATE (in this case, VL=3)
+ svstate = SVP64State()
+ svstate.vl[0:7] = 3 # VL
+ svstate.maxvl[0:7] = 3 # MAXVL
+ print("SVSTATE", bin(svstate.spr.asint()))
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ expected_regs[5] = 0xffff_ffff_ffff_ff90 # 1st bit of r3 is 1
+ expected_regs[6] = 0x0 # skip
+ expected_regs[7] = 0xffff_ffff_ffff_ff91 # 3nd bit of r3 is 1
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate)
+ self._check_regs(sim, expected_regs)
+
+ def test_intpred_twinpred(self):
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11
+ # src r3=0b101 Y N Y
+ # |
+ # +-----+
+ # |
+ # dest ~r3=0b010 N Y N
+
+ isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+ lst = list(isa)
+ print("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[3] = 0b101 # predicate mask
+ initial_regs[9] = 0x90 # source r3 is 0b101 so this will be used
+ initial_regs[10] = 0x91 # this gets skipped
+ initial_regs[11] = 0x92 # VL loop runs out before we can use it
+ # SVSTATE (in this case, VL=3)
+ svstate = SVP64State()
+ svstate.vl[0:7] = 3 # VL
+ svstate.maxvl[0:7] = 3 # MAXVL
+ print("SVSTATE", bin(svstate.spr.asint()))
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ expected_regs[5] = 0x0 # dest ~r3 is 0b010: skip
+ expected_regs[6] = 0xffff_ffff_ffff_ff90 # 2nd bit of ~r3 is 1
+ expected_regs[7] = 0x0 # dest ~r3 is 0b010: skip
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate)
+ self._check_regs(sim, expected_regs)
+
+ # checks that we are able to resume in the middle of a VL loop,
+ # after an interrupt, or after the user has updated src/dst step
+ # let's assume the user has prepared src/dst step before running this
+ # vector instruction
+ def test_intpred_reentrant(self):
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11 12
+ # srcstep=1 v
+ # src r3=0b0101 Y N Y N
+ # : |
+ # + - - + |
+ # : +-------+
+ # : |
+ # dest ~r3=0b1010 N Y N Y
+ # dststep=2 ^
+
+ isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+ lst = list(isa)
+ print("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[3] = 0b0101 # mask
+ initial_regs[9] = 0x90 # srcstep starts at 2, so this gets skipped
+ initial_regs[10] = 0x91 # skip
+ initial_regs[11] = 0x92 # this will be used
+ initial_regs[12] = 0x93 # skip
+
+ # SVSTATE (in this case, VL=4)
+ svstate = SVP64State()
+ svstate.vl[0:7] = 4 # VL
+ svstate.maxvl[0:7] = 4 # MAXVL
+ # set src/dest step on the middle of the loop
+ svstate.srcstep[0:7] = 1
+ svstate.dststep[0:7] = 2
+ print("SVSTATE", bin(svstate.spr.asint()))
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ expected_regs[5] = 0x0 # skip
+ expected_regs[6] = 0x0 # dststep starts at 3, so this gets skipped
+ expected_regs[7] = 0x0 # skip
+ expected_regs[8] = 0xffff_ffff_ffff_ff92 # this will be used
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate)
+ self._check_regs(sim, expected_regs)
+
def run_tst_program(self, prog, initial_regs=None,
svstate=None,
initial_cr=0):
projects / soc.git / blobdiff