Add test_branch_loop_ctr

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index be41b5ccf1d73d7057834f7b09c6835320662161..ca17eef4d328801ab0926ac27df02c95feca6f1e 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -1,22 +1,22 @@
 from enum import Enum, unique
 import csv
 import os
-import requests
+from os.path import dirname, join
+from collections import namedtuple
 
+def find_wiki_file(name):
+    filedir = os.path.dirname(os.path.abspath(__file__))
+    basedir = dirname(dirname(dirname(filedir)))
+    tabledir = join(basedir, 'libreriscv')
+    tabledir = join(tabledir, 'openpower')
+    tabledir = join(tabledir, 'isatables')
 
-def download_wiki_file(name):
-    file_dir = os.path.dirname(os.path.realpath(__file__))
-    file_path = os.path.join(file_dir, name)
-    if not os.path.isfile(file_path):
-        url = 'https://libre-riscv.org/openpower/isatables/' + name
-        r = requests.get(url, allow_redirects=True)
-        with open(file_path, 'w') as outfile:
-            outfile.write(r.content.decode("utf-8"))
+    file_path = join(tabledir, name)
     return file_path
 
 
 def get_csv(name):
-    file_path = download_wiki_file(name)
+    file_path = find_wiki_file(name)
     with open(file_path, 'r') as csvfile:
         reader = csv.DictReader(csvfile)
         return list(reader)
@@ -29,9 +29,10 @@ single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
 
 # default values for fields in the table
 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
-                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
-                   'ldst len': 'NONE',
-                   'rc' : 'NONE', 'cry in' : 'ZERO', 'form': 'NONE'}
+                  'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
+                  'ldst len': 'NONE',
+                  'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
+
 
 def get_signal_name(name):
     if name[0].isdigit():
@@ -79,10 +80,10 @@ class Form(Enum):
     Z23 = 28
 
 
-
+# Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique
 class InternalOp(Enum):
-    OP_ILLEGAL = 0
+    OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
     OP_NOP = 1
     OP_ADD = 2
     OP_ADDPCIS = 3
@@ -155,9 +156,9 @@ class InternalOp(Enum):
 
 @unique
 class In1Sel(Enum):
-    RA = 0
-    RA_OR_ZERO = 1
-    NONE = 2
+    NONE = 0
+    RA = 1
+    RA_OR_ZERO = 2
     SPR = 3
 
 
@@ -214,21 +215,26 @@ class CryIn(Enum):
     ONE = 1
     CA = 2
 
-@unique
-class SPR(Enum):
-    XER    = 1
-    LR     = 8
-    CTR    = 9
-    TB     = 268
-    SRR0   = 26
-    SRR1   = 27
-    HSRR0  = 314
-    HSRR1  = 315
-    SPRG0  = 272
-    SPRG1  = 273
-    SPRG2  = 274
-    SPRG3  = 275
-    SPRG3U = 259
-    HSPRG0 = 304
-    HSPRG1 = 305
 
+# SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
+# http://libre-riscv.org/openpower/isatables/sprs.csv
+# http://bugs.libre-riscv.org/show_bug.cgi?id=261
+
+spr_csv = get_csv("sprs.csv")
+spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length')
+spr_dict = {}
+for row in spr_csv:
+    info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
+                    priv_mfspr=row['priv_mfspr'], length=int(row['len']))
+    spr_dict[int(row['Idx'])] = info
+fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
+SPR = Enum('SPR', fields)
+
+
+XER_bits = {
+    'SO': 32,
+    'OV': 33,
+    'CA': 34,
+    'OV32': 44,
+    'CA32': 45
+    }