comment update

[soc.git] / src / soc / decoder / power_fieldsn.py

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index eefe929ea41290ea65aef4caaa85524780c41e40..852dd15b079cc88a1b555f71d216107ce2d9c7a1 100644 (file)
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -2,6 +2,7 @@ from collections import OrderedDict
 from soc.decoder.power_fields import DecodeFields, BitRange
 from nmigen import Module, Elaboratable, Signal, Cat
 from nmigen.cli import rtlil
+from copy import deepcopy
 
 
 class SignalBitRange(BitRange):
@@ -9,6 +10,15 @@ class SignalBitRange(BitRange):
         BitRange.__init__(self)
         self.signal = signal
 
+    def __deepcopy__(self, memo):
+        signal = deepcopy(self.signal, memo)
+        retval = SignalBitRange(signal=signal)
+        for k, v in self.items():
+            k = deepcopy(k, memo)
+            v = deepcopy(v, memo)
+            retval[k] = v
+        return retval
+
     def _rev(self, k):
         width = self.signal.width
         return width-1-k