decoder immediate b split out to DecodeBImm

[soc.git] / src / soc / decoder / power_fieldsn.py

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index 1a639a3d6969f565ff86ab2cccdf027b6d5a5919..eefe929ea41290ea65aef4caaa85524780c41e40 100644 (file)
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -10,7 +10,7 @@ class SignalBitRange(BitRange):
         self.signal = signal
 
     def _rev(self, k):
-        width = self.signal.shape()[0]
+        width = self.signal.width
         return width-1-k
 
     def __getitem__(self, subs):
@@ -29,17 +29,16 @@ class SignalBitRange(BitRange):
             if stop < 0:
                 stop = len(self) + stop + 1
             for t in range(start, stop, step):
-                t = len(self) - 1 - t # invert field back
+                t = len(self) - 1 - t  # invert field back
                 k = OrderedDict.__getitem__(self, t)
-                res.append(self.signal[self._rev(k)]) # reverse-order here
+                res.append(self.signal[self._rev(k)])  # reverse-order here
             return Cat(*res)
         else:
             if subs < 0:
                 subs = len(self) + subs
-            subs = len(self) - 1 - subs # invert field back
+            subs = len(self) - 1 - subs  # invert field back
             k = OrderedDict.__getitem__(self, subs)
-            return self.signal[self._rev(k)] # reverse-order here
-
+            return self.signal[self._rev(k)]  # reverse-order here
 
 
 class SigDecode(Elaboratable):
@@ -48,28 +47,23 @@ class SigDecode(Elaboratable):
         self.opcode_in = Signal(width, reset_less=False)
         self.df = DecodeFields(SignalBitRange, [self.opcode_in])
         self.df.create_specs()
-        self.x_s = Signal(len(self.df.FormX.S), reset_less=True)
-        self.x_sh = Signal(len(self.df.FormX.SH), reset_less=True)
-        self.dq_xs_s = Signal(len(self.df.FormDQ.SX_S), reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
-        comb += self.x_s.eq(self.df.FormX.S[0])
-        comb += self.x_sh.eq(self.df.FormX.SH[0:-1])
-        comb += self.dq_xs_s.eq(self.df.FormDQ.SX_S[0:-1])
         return m
 
     def ports(self):
-        return [self.opcode_in, self.x_s, self.x_sh]
+        return [self.opcode_in]
+
 
 def create_sigdecode():
     s = SigDecode(32)
     return s
 
+
 if __name__ == '__main__':
     sigdecode = create_sigdecode()
     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
     with open("decoder.il", "w") as f:
         f.write(vl)
-