Fix bug in GAS test where it would load and update the same register

[soc.git] / src / soc / decoder / test / test_decoder_gas.py

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index 0003e2e6315297765e5d5097a347c340c6a2a938..be3f42b7ba407c1efc4d5da347308e5f963b11b8 100644 (file)
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -33,7 +33,7 @@ class Checker:
             imm = self.imm << 16
             sign_bit = 1 << 31
             return (imm & (sign_bit-1)) - (imm & sign_bit)
-        
+
 
 class RegRegOp:
     def __init__(self):
@@ -152,6 +152,8 @@ class LdStOp(Checker):
         self.opcode = self.ops[self.opcodestr]
         self.r1 = Register(random.randrange(32))
         self.r2 = Register(random.randrange(1, 32))
+        while self.r2.num == self.r1.num:
+            self.r2 = Register(random.randrange(1, 32))
         self.imm = random.randrange(32767)
 
     def generate_instruction(self):
@@ -213,7 +215,7 @@ class CmpRegOp:
     def check_results(self, pdecode2):
         r1sel = yield pdecode2.e.read_reg1.data
         r2sel = yield pdecode2.e.read_reg2.data
-        crsel = yield pdecode2.dec.BF[0:-1]
+        crsel = yield pdecode2.dec.BF
 
         assert(r1sel == self.r1.num)
         assert(r2sel == self.r2.num)
@@ -253,11 +255,11 @@ class RotateOp:
         dec = pdecode2.dec
 
         if "i" in self.opcodestr:
-            shift = yield dec.SH[0:-1]
+            shift = yield dec.SH
         else:
             shift = yield pdecode2.e.read_reg2.data
-        mb = yield dec.MB[0:-1]
-        me = yield dec.ME[0:-1]
+        mb = yield dec.MB
+        me = yield dec.ME
 
         assert(r1sel == self.r1.num)
         assert(r2sel == self.r2.num)
@@ -298,7 +300,7 @@ class Branch:
             assert(lk == 1)
         else:
             assert(lk == 0)
-        aa = yield pdecode2.dec.AA[0:-1]
+        aa = yield pdecode2.dec.AA
         if "a" in self.opcodestr:
             assert(aa == 1)
         else:
@@ -332,8 +334,8 @@ class BranchCond:
 
     def check_results(self, pdecode2):
         imm = yield pdecode2.e.imm_data.data
-        bo = yield pdecode2.dec.BO[0:-1]
-        bi = yield pdecode2.dec.BI[0:-1]
+        bo = yield pdecode2.dec.BO
+        bi = yield pdecode2.dec.BI
 
         assert(imm == self.addr)
         assert(bo == self.bo)
@@ -343,7 +345,7 @@ class BranchCond:
             assert(lk == 1)
         else:
             assert(lk == 0)
-        aa = yield pdecode2.dec.AA[0:-1]
+        aa = yield pdecode2.dec.AA
         if "a" in self.opcodestr:
             assert(aa == 1)
         else:
@@ -375,8 +377,8 @@ class BranchRel:
         return string
 
     def check_results(self, pdecode2):
-        bo = yield pdecode2.dec.BO[0:-1]
-        bi = yield pdecode2.dec.BI[0:-1]
+        bo = yield pdecode2.dec.BO
+        bi = yield pdecode2.dec.BI
 
         assert(bo == self.bo)
         assert(bi == self.bi)