Convert yet another few tests to be able to use latest cxxsim

[soc.git] / src / soc / decoder / test / test_power_decoder.py

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index 1e5aa8fc51ebc4817dc1fcd92477762a29aa20cd..0a18c77bbe329cb0f28ece7bc826af9084acfbe0 100644 (file)
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import os