test_dcbz_pi.py: dcbz now working

[soc.git] / src / soc / experiment / alu_fsm.py

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 468ddefe74035ca67b99a003bca4e3c203e8f67b..3fb1c6cfe595d627506a941f87f5d39ab2bb5079 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -17,17 +17,15 @@ The basic rules are:
 """
 
 from nmigen import Elaboratable, Signal, Module, Cat
-from nmigen.back.pysim import Simulator
 from nmigen.cli import rtlil
 from math import log2
-import os
 
 from nmutil.iocontrol import PrevControl, NextControl
 
 from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
 
 from nmutil.gtkw import write_gtkw
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim)
 
 
 class CompFSMOpSubset(CompOpSubsetBase):
@@ -38,7 +36,6 @@ class CompFSMOpSubset(CompOpSubsetBase):
         super().__init__(layout, name=name)
 
 
-
 class Dummy:
     pass
 
@@ -64,7 +61,7 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.ctx = Dummy() # comply with CompALU API
+            self.ctx = Dummy()  # comply with CompALU API
 
         def _get_data(self):
             return [self.data, self.shift]
@@ -215,72 +212,36 @@ def test_shifter():
     with open("test_shifter.il", "w") as f:
         f.write(il)
 
-    engine = os.environ.get("NMIGEN_SIM_MODE")
-
     gtkwave_style = {
         'in': {'color': 'orange'},
         'out': {'color': 'yellow'},
     }
 
-    # Allow for differences in signal naming among the engines
-
-    if engine == "cxxsim":
-        module = "shf"
-        gtkwave_desc = [
-            'clk',
-            {'comment': 'Shifter Demonstration'},
-            ('prev port', [
-                ('op__sdir', 'in'),
-                ('p_data_i[7:0]', 'in'),
-                ('p_shift_i[7:0]', 'in'),
-                ('p_valid_i', 'in'),
-                ('p_p_ready_o', 'out'),
-            ]),
-            ('internal', [
-                'fsm_state[1:0]',
-                'count[3:0]',
-                'shift_reg[7:0]',
-            ]),
-            ('next port', [
-                ('n_data_o[7:0]', 'out'),
-                ('n_n_valid_o', 'out'),
-                ('n_ready_i', 'in'),
-            ]),
-        ]
-    else:
-        module = "top.shf"
-        gtkwave_desc = [
-            'clk',
-            {'comment': 'Shifter Demonstration'},
-            ('prev port', [
-                ('op__sdir', 'in'),
-                ('p_data_i[7:0]', 'in'),
-                ('p_shift_i[7:0]', 'in'),
+    gtkwave_desc = [
+        'clk',
+        {'comment': 'Shifter Demonstration'},
+        ('prev port', [
+            ('op__sdir', 'in'),
+            ('p_data_i[7:0]', 'in'),
+            ('p_shift_i[7:0]', 'in'),
+            ({'submodule': 'p'}, [
                 ('p_valid_i', 'in'),
-                ('p_ready_o', 'out'),
-            ]),
-            ('internal', [
-                'fsm_state',
-                'count[3:0]',
-                'shift_reg[7:0]',
-            ]),
-            ('next port', [
-                ('n_data_o[7:0]', 'out'),
+                ('p_ready_o', 'out')])]),
+        ('internal', [
+            'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
+            'count[3:0]',
+            'shift_reg[7:0]']),
+        ('next port', [
+            ('n_data_o[7:0]', 'out'),
+            ({'submodule': 'n'}, [
                 ('n_valid_o', 'out'),
-                ('n_ready_i', 'in'),
-            ]),
-        ]
+                ('n_ready_i', 'in')])])]
 
     write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
                gtkwave_desc,  gtkwave_style,
-               module=module, loc=__file__, base='dec')
-
-    if engine:
-        sim = Simulator(m, engine=engine)
-    else:
-        # old developer versions do not have the engine parameter
-        sim = Simulator(m)
+               module='top.shf', loc=__file__, base='dec')
 
+    sim = Simulator(m)
     sim.add_clock(1e-6)
 
     def send(data, shift, direction):
@@ -293,9 +254,6 @@ def test_shifter():
         # wait for p.ready_o to be asserted
         while not (yield dut.p.ready_o):
             yield
-        # show current operation operation
-        # force dump of the above message by toggling the
-        # underlying signal
         # clear input data and negate p.valid_i
         yield dut.p.valid_i.eq(0)
         yield dut.p.data_i.data.eq(0)
@@ -315,7 +273,6 @@ def test_shifter():
         yield dut.n.ready_i.eq(0)
         # check result
         assert result == expected
-        # finish displaying the current operation
 
     def producer():
         # 13 >> 2
@@ -323,8 +280,6 @@ def test_shifter():
         # 3 << 4
         yield from send(3, 4, 0)
         # 21 << 0
-        # use a debug signal to mark an interesting operation
-        # in this case, it is a shift by zero
         yield from send(21, 0, 0)
 
     def consumer():
@@ -335,8 +290,6 @@ def test_shifter():
         # 3 << 4 = 48
         yield from receive(48)
         # 21 << 0 = 21
-        # you can look for the rising edge of this signal to quickly
-        # locate this point in the traces
         yield from receive(21)
 
     sim.add_sync_process(producer)