test_dcbz_pi.py: dcbz now working

[soc.git] / src / soc / experiment / alu_fsm.py

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 70dbb9bb13a620cbd837e7c236dbe155a5f78e25..3fb1c6cfe595d627506a941f87f5d39ab2bb5079 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -19,16 +19,13 @@ The basic rules are:
 from nmigen import Elaboratable, Signal, Module, Cat
 from nmigen.cli import rtlil
 from math import log2
-import os
 
 from nmutil.iocontrol import PrevControl, NextControl
 
 from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
 
 from nmutil.gtkw import write_gtkw
-from nmutil.sim_tmp_alternative import Simulator, is_engine_pysim, \
-     nmigen_sim_top_module
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim)
 
 
 class CompFSMOpSubset(CompOpSubsetBase):
@@ -39,7 +36,6 @@ class CompFSMOpSubset(CompOpSubsetBase):
         super().__init__(layout, name=name)
 
 
-
 class Dummy:
     pass
 
@@ -65,7 +61,7 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.ctx = Dummy() # comply with CompALU API
+            self.ctx = Dummy()  # comply with CompALU API
 
         def _get_data(self):
             return [self.data, self.shift]
@@ -228,25 +224,22 @@ def test_shifter():
             ('op__sdir', 'in'),
             ('p_data_i[7:0]', 'in'),
             ('p_shift_i[7:0]', 'in'),
-            ('p_valid_i', 'in'),
-            ('p_ready_o' if is_engine_pysim() else 'p_p_ready_o', 'out'),
-        ]),
+            ({'submodule': 'p'}, [
+                ('p_valid_i', 'in'),
+                ('p_ready_o', 'out')])]),
         ('internal', [
             'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
             'count[3:0]',
-            'shift_reg[7:0]',
-        ]),
+            'shift_reg[7:0]']),
         ('next port', [
             ('n_data_o[7:0]', 'out'),
-            ('n_valid_o' if is_engine_pysim() else 'n_n_valid_o', 'out'),
-            ('n_ready_i', 'in'),
-        ]),
-    ]
+            ({'submodule': 'n'}, [
+                ('n_valid_o', 'out'),
+                ('n_ready_i', 'in')])])]
 
-    module = nmigen_sim_top_module + "shf"
     write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
                gtkwave_desc,  gtkwave_style,
-               module=module, loc=__file__, base='dec')
+               module='top.shf', loc=__file__, base='dec')
 
     sim = Simulator(m)
     sim.add_clock(1e-6)
@@ -261,9 +254,6 @@ def test_shifter():
         # wait for p.ready_o to be asserted
         while not (yield dut.p.ready_o):
             yield
-        # show current operation operation
-        # force dump of the above message by toggling the
-        # underlying signal
         # clear input data and negate p.valid_i
         yield dut.p.valid_i.eq(0)
         yield dut.p.data_i.data.eq(0)
@@ -283,7 +273,6 @@ def test_shifter():
         yield dut.n.ready_i.eq(0)
         # check result
         assert result == expected
-        # finish displaying the current operation
 
     def producer():
         # 13 >> 2
@@ -291,8 +280,6 @@ def test_shifter():
         # 3 << 4
         yield from send(3, 4, 0)
         # 21 << 0
-        # use a debug signal to mark an interesting operation
-        # in this case, it is a shift by zero
         yield from send(21, 0, 0)
 
     def consumer():
@@ -303,8 +290,6 @@ def test_shifter():
         # 3 << 4 = 48
         yield from receive(48)
         # 21 << 0 = 21
-        # you can look for the rising edge of this signal to quickly
-        # locate this point in the traces
         yield from receive(21)
 
     sim.add_sync_process(producer)