icache.py fix several subtle bugs that were lines that I had missed from

[soc.git] / src / soc / experiment / alu_fsm.py

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 4a6b8902645963c6beb77c2031f12c83d899df5e..46593dd14b5c906c48fc2ee5fbb6ebe61f4b151b 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -17,19 +17,16 @@ The basic rules are:
 """
 
 from nmigen import Elaboratable, Signal, Module, Cat
-cxxsim = False
-if cxxsim:
-    from nmigen.sim.cxxsim import Simulator, Settle
-else:
-    from nmigen.back.pysim import Simulator, Settle
 from nmigen.cli import rtlil
 from math import log2
+
 from nmutil.iocontrol import PrevControl, NextControl
 
 from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
 
 from nmutil.gtkw import write_gtkw
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim,
+                                        nmigen_sim_top_module)
 
 
 class CompFSMOpSubset(CompOpSubsetBase):
@@ -40,7 +37,6 @@ class CompFSMOpSubset(CompOpSubsetBase):
         super().__init__(layout, name=name)
 
 
-
 class Dummy:
     pass
 
@@ -66,7 +62,7 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.ctx = Dummy() # comply with CompALU API
+            self.ctx = Dummy()  # comply with CompALU API
 
         def _get_data(self):
             return [self.data, self.shift]
@@ -230,23 +226,24 @@ def test_shifter():
             ('p_data_i[7:0]', 'in'),
             ('p_shift_i[7:0]', 'in'),
             ('p_valid_i', 'in'),
-            ('p_ready_o', 'out'),
+            ('p_ready_o' if is_engine_pysim() else 'p_p_ready_o', 'out'),
         ]),
         ('internal', [
-            'fsm_state',
+            'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
             'count[3:0]',
             'shift_reg[7:0]',
         ]),
         ('next port', [
             ('n_data_o[7:0]', 'out'),
-            ('n_valid_o', 'out'),
+            ('n_valid_o' if is_engine_pysim() else 'n_n_valid_o', 'out'),
             ('n_ready_i', 'in'),
         ]),
     ]
 
+    module = nmigen_sim_top_module + "shf"
     write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
                gtkwave_desc,  gtkwave_style,
-               module="top.shf", loc=__file__, base='dec')
+               module=module, loc=__file__, base='dec')
 
     sim = Simulator(m)
     sim.add_clock(1e-6)