"""
from nmigen import Elaboratable, Signal, Module, Cat
-from nmigen.back.pysim import Simulator
from nmigen.cli import rtlil
from math import log2
+
from nmutil.iocontrol import PrevControl, NextControl
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
+
+from nmutil.gtkw import write_gtkw
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim,
+ nmigen_sim_top_module)
class CompFSMOpSubset(CompOpSubsetBase):
def __init__(self, name=None):
- layout = (('dir', 1),
+ layout = (('sdir', 1),
)
super().__init__(layout, name=name)
-
class Dummy:
pass
* On POWER, range is 0 to 63 for 32-bit,
* and 0 to 127 for 64-bit.
* Other values wrap around.
- * p.data_i.sdir: shift direction (0 = left, 1 = right)
+
+ Operation type
+ * op.sdir: shift direction (0 = left, 1 = right)
Next port data:
* n.data_o.data: shifted value
def __init__(self, width):
self.data = Signal(width, name="p_data_i")
self.shift = Signal(width, name="p_shift_i")
- self.sdir = Signal(name="p_sdir_i")
- self.ctx = Dummy() # comply with CompALU API
+ self.ctx = Dummy() # comply with CompALU API
def _get_data(self):
return [self.data, self.shift]
self.n.data_o = Shifter.NextData(width)
# more pieces to make this example class comply with the CompALU API
- self.op = CompFSMOpSubset()
+ self.op = CompFSMOpSubset(name="op")
self.p.data_i.ctx.op = self.op
self.i = self.p.data_i._get_data()
self.out = self.n.data_o._get_data()
next_count.eq(self.p.data_i.shift),
]
# capture the direction bit as well
- m.d.sync += direction.eq(self.p.data_i.sdir)
+ m.d.sync += direction.eq(self.op.sdir)
with m.If(self.p.valid_i):
# Leave IDLE when data arrives
with m.If(next_count == 0):
return m
def __iter__(self):
+ yield self.op.sdir
yield self.p.data_i.data
yield self.p.data_i.shift
- yield self.p.data_i.sdir
yield self.p.valid_i
yield self.p.ready_o
yield self.n.ready_i
il = rtlil.convert(dut, ports=dut.ports())
with open("test_shifter.il", "w") as f:
f.write(il)
+
+ gtkwave_style = {
+ 'in': {'color': 'orange'},
+ 'out': {'color': 'yellow'},
+ }
+
+ gtkwave_desc = [
+ 'clk',
+ {'comment': 'Shifter Demonstration'},
+ ('prev port', [
+ ('op__sdir', 'in'),
+ ('p_data_i[7:0]', 'in'),
+ ('p_shift_i[7:0]', 'in'),
+ ('p_valid_i', 'in'),
+ ('p_ready_o' if is_engine_pysim() else 'p_p_ready_o', 'out'),
+ ]),
+ ('internal', [
+ 'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
+ 'count[3:0]',
+ 'shift_reg[7:0]',
+ ]),
+ ('next port', [
+ ('n_data_o[7:0]', 'out'),
+ ('n_valid_o' if is_engine_pysim() else 'n_n_valid_o', 'out'),
+ ('n_ready_i', 'in'),
+ ]),
+ ]
+
+ module = nmigen_sim_top_module + "shf"
+ write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
+ gtkwave_desc, gtkwave_style,
+ module=module, loc=__file__, base='dec')
+
sim = Simulator(m)
sim.add_clock(1e-6)
# present input data and assert valid_i
yield dut.p.data_i.data.eq(data)
yield dut.p.data_i.shift.eq(shift)
- yield dut.p.data_i.sdir.eq(direction)
+ yield dut.op.sdir.eq(direction)
yield dut.p.valid_i.eq(1)
yield
# wait for p.ready_o to be asserted
while not (yield dut.p.ready_o):
yield
+ # show current operation operation
+ # force dump of the above message by toggling the
+ # underlying signal
# clear input data and negate p.valid_i
yield dut.p.valid_i.eq(0)
yield dut.p.data_i.data.eq(0)
yield dut.p.data_i.shift.eq(0)
- yield dut.p.data_i.sdir.eq(0)
+ yield dut.op.sdir.eq(0)
def receive(expected):
# signal readiness to receive data
yield dut.n.ready_i.eq(0)
# check result
assert result == expected
+ # finish displaying the current operation
def producer():
# 13 >> 2
# 3 << 4
yield from send(3, 4, 0)
# 21 << 0
+ # use a debug signal to mark an interesting operation
+ # in this case, it is a shift by zero
yield from send(21, 0, 0)
def consumer():
# 3 << 4 = 48
yield from receive(48)
# 21 << 0 = 21
+ # you can look for the rising edge of this signal to quickly
+ # locate this point in the traces
yield from receive(21)
sim.add_sync_process(producer)
sim.add_sync_process(consumer)
- sim_writer = sim.write_vcd(
- "test_shifter.vcd",
- "test_shifter.gtkw",
- traces=dut.ports()
- )
+ sim_writer = sim.write_vcd("test_shifter.vcd")
with sim_writer:
sim.run()
projects / soc.git / blobdiff