('output_cr', 1),
('is_32bit', 1),
('is_signed', 1),
+ ('data_len', 4), # TODO: should be in separate CompLDSTSubset
('byte_reverse', 1),
('sign_extend', 1))
self.output_cr.reset_less = True
self.is_32bit.reset_less = True
self.is_signed.reset_less = True
+ self.data_len.reset_less = True
self.byte_reverse.reset_less = True
self.sign_extend.reset_less = True
self.output_cr,
self.is_32bit,
self.is_signed,
+ self.data_len,
self.byte_reverse,
self.sign_extend,
]
self.n_valid_o = Signal()
self.counter = Signal(4)
self.op = Signal(2)
- self.a = Signal(width)
- self.b = Signal(width)
- self.o = Signal(width)
+ i = []
+ i.append(Signal(width, name="i1"))
+ i.append(Signal(width, name="i2"))
+ self.i = Array(i)
+ self.a, self.b = i[0], i[1]
+ self.out = Array([Signal(width)])
+ self.o = self.out[0]
self.width = width
def elaborate(self, platform):