get compldst.py unit test up and running after modifications to ALU

[soc.git] / src / soc / experiment / alu_hier.py

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 9fd21c493a486199e09d02cd97d18e816570ff98..0021c0793c6cf874060148ff83c0cee6720b6f8d 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -9,13 +9,13 @@ A "real" integer ALU would place the answers onto the output bus after
 only one cycle (sync)
 """
 
-from nmigen import Elaboratable, Signal, Module, Const, Mux
+from nmigen import Elaboratable, Signal, Module, Const, Mux, Array
 from nmigen.hdl.rec import Record, Layout
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 from nmigen.compat.sim import run_simulation
 
-from soc.decoder.power_enums import InternalOp, CryIn
+from soc.decoder.power_enums import InternalOp, Function, CryIn
 
 import operator
 
@@ -24,10 +24,12 @@ class CompALUOpSubset(Record):
     """CompALUOpSubset
 
     a copy of the relevant subset information from Decode2Execute1Type
-    needed for ALU operations.
+    needed for ALU operations.  use with eq_from_execute1 (below) to
+    grab subsets.
     """
-    def __init__(self):
+    def __init__(self, name=None):
         layout = (('insn_type', InternalOp),
+                  ('fn_unit', Function),
                   ('nia', 64),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                     #'cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
@@ -43,13 +45,15 @@ class CompALUOpSubset(Record):
                   ('output_cr', 1),
                   ('is_32bit', 1),
                   ('is_signed', 1),
+                  ('data_len', 4), # TODO: should be in separate CompLDSTSubset
                   ('byte_reverse', 1),
                   ('sign_extend', 1))
 
-        Record.__init__(self, Layout(layout))
+        Record.__init__(self, Layout(layout), name=name)
 
         # grrr.  Record does not have kwargs
         self.insn_type.reset_less = True
+        self.fn_unit.reset_less = True
         self.nia.reset_less = True
         #self.cr = Signal(32, reset_less = True
         #self.xerc = XerBits(
@@ -62,9 +66,19 @@ class CompALUOpSubset(Record):
         self.output_cr.reset_less = True
         self.is_32bit.reset_less = True
         self.is_signed.reset_less = True
+        self.data_len.reset_less = True
         self.byte_reverse.reset_less = True
         self.sign_extend.reset_less = True
 
+    def eq_from_execute1(self, other):
+        """ use this to copy in from Decode2Execute1Type
+        """
+        res = []
+        for fname, sig in self.fields.items():
+            eqfrom = other.fields[fname]
+            res.append(sig.eq(eqfrom))
+        return res
+
     def ports(self):
         return [self.insn_type,
                 self.nia,
@@ -79,10 +93,12 @@ class CompALUOpSubset(Record):
                 self.output_cr,
                 self.is_32bit,
                 self.is_signed,
+                self.data_len,
                 self.byte_reverse,
                 self.sign_extend,
         ]
 
+
 class Adder(Elaboratable):
     def __init__(self, width):
         self.invert_a = Signal()
@@ -146,9 +162,13 @@ class ALU(Elaboratable):
         self.n_valid_o = Signal()
         self.counter   = Signal(4)
         self.op  = CompALUOpSubset()
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
+        i = []
+        i.append(Signal(width, name="i1"))
+        i.append(Signal(width, name="i2"))
+        self.i = Array(i)
+        self.a, self.b = i[0], i[1]
+        self.out = Array([Signal(width)])
+        self.o = self.out[0]
         self.width = width
 
     def elaborate(self, platform):
@@ -191,18 +211,19 @@ class ALU(Elaboratable):
                 # NOTE: all of these are fake, just something to test
 
                 # MUL, to take 5 instructions
-                with m.If(self.op.insn_type == InternalOp.OP_MUL_L64.value):
+                with m.If(self.op.insn_type == InternalOp.OP_MUL_L64):
                     m.d.sync += self.counter.eq(5)
                 # SHIFT to take 7
-                with m.Elif(self.op.insn_type == InternalOp.OP_SHR.value):
+                with m.Elif(self.op.insn_type == InternalOp.OP_SHR):
                     m.d.sync += self.counter.eq(7)
-                # SUB to take 1, straight away
-                with m.If(self.op.insn_type == InternalOp.OP_ADD.value):
-                    m.d.sync += self.counter.eq(1)
-                    m.d.comb += go_now.eq(1)
-                # ADD to take 2
+                # ADD/SUB to take 2, straight away
+                with m.If(self.op.insn_type == InternalOp.OP_ADD):
+                    m.d.sync += self.counter.eq(3)
+                # others to take 1, straight away
                 with m.Else():
-                    m.d.sync += self.counter.eq(2)
+                    m.d.comb += go_now.eq(1)
+                    m.d.sync += self.counter.eq(1)
+
         with m.Else():
             # input says no longer valid, so drop ready as well.
             # a "proper" ALU would have had to sync in the opcode and a/b ops
@@ -255,9 +276,13 @@ class BranchALU(Elaboratable):
         self.n_valid_o = Signal()
         self.counter   = Signal(4)
         self.op  = Signal(2)
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
+        i = []
+        i.append(Signal(width, name="i1"))
+        i.append(Signal(width, name="i2"))
+        self.i = Array(i)
+        self.a, self.b = i[0], i[1]
+        self.out = Array([Signal(width)])
+        self.o = self.out[0]
         self.width = width
 
     def elaborate(self, platform):