i.append(Signal(width, name="i2"))
self.i = Array(i)
self.a, self.b = i[0], i[1]
- self.out = Array([Data(width, name="alu_o")])
+ out = []
+ out.append(Data(width, name="alu_o"))
+ out.append(Data(width, name="alu_cr"))
+ self.out = Array(out)
self.o = self.out[0]
+ self.cr = self.out[1]
self.width = width
# more "look like nmutil pipeline API"
self.p.data_i.ctx.op = self.op
self.p.data_i.a = self.a
self.p.data_i.b = self.b
self.n.data_o.o = self.o
+ self.n.data_o.cr = self.cr
def elaborate(self, platform):
m = Module()
# hold the ALU result until ready_o is asserted
alu_r = Signal(self.width)
- # NOP doesn't output anything
- with m.If(self.op.insn_type != MicrOp.OP_NOP):
+ # output masks
+ # NOP and ILLEGAL don't output anything
+ with m.If((self.op.insn_type != MicrOp.OP_NOP) &
+ (self.op.insn_type != MicrOp.OP_ILLEGAL)):
m.d.comb += self.o.ok.eq(1)
+ # CR is output when rc bit is active
+ m.d.comb += self.cr.ok.eq(self.op.rc.rc)
+
with m.If(alu_idle):
with m.If(self.p.valid_i):
with m.Elif(alu_done):
m.d.comb += self.o.data.eq(alu_r)
+ # determine condition register bits based on the data output value
+ with m.If(~self.o.data.any()):
+ m.d.comb += self.cr.data.eq(0b001)
+ with m.Elif(self.o.data[-1]):
+ m.d.comb += self.cr.data.eq(0b010)
+ with m.Else():
+ m.d.comb += self.cr.data.eq(0b100)
+
return m
def __iter__(self):
sim = Simulator(m)
sim.add_clock(1e-6)
- def send(a, b, op, inv_a=0):
+ def send(a, b, op, inv_a=0, rc=0):
# present input data and assert valid_i
yield dut.a.eq(a)
yield dut.b.eq(b)
yield dut.op.insn_type.eq(op)
yield dut.op.invert_in.eq(inv_a)
+ yield dut.op.rc.rc.eq(rc)
yield dut.p.valid_i.eq(1)
yield
# wait for ready_o to be asserted
yield dut.b.eq(0)
yield dut.op.insn_type.eq(0)
yield dut.op.invert_in.eq(0)
+ yield dut.op.rc.rc.eq(0)
def receive():
# signal readiness to receive data
# wait for valid_o to be asserted
while not (yield dut.n.valid_o):
yield
- # read result
+ # read results
result = yield dut.o.data
+ cr = yield dut.cr.data
# negate ready_i
# if receive is called again immediately afterwards, there will be no
# visible transition (it will not be negated, after all)
yield dut.n.ready_i.eq(0)
- return result
+ return result, cr
def producer():
# send a few test cases, interspersed with wait states
yield
yield
# 2 * 3
- yield from send(2, 3, MicrOp.OP_MUL_L64)
- # (-5) + 3
- yield from send(5, 3, MicrOp.OP_ADD, inv_a=1)
+ yield from send(2, 3, MicrOp.OP_MUL_L64, rc=1)
+ # (-6) + 3
+ yield from send(5, 3, MicrOp.OP_ADD, inv_a=1, rc=1)
yield
# 5 - 3
# note that this is a zero-delay operation
- yield from send(5, 3, MicrOp.OP_NOP)
+ yield from send(5, 3, MicrOp.OP_CMP)
yield
yield
+ # NOP
+ yield from send(5, 3, MicrOp.OP_NOP)
# 13 >> 2
yield from send(13, 2, MicrOp.OP_SHR)
# sign extent 13
yield from send(13, 2, MicrOp.OP_EXTS)
# sign extend -128 (8 bits)
- yield from send(0x80, 2, MicrOp.OP_EXTS)
+ yield from send(0x80, 2, MicrOp.OP_EXTS, rc=1)
# sign extend -128 (8 bits)
yield from send(2, 0x80, MicrOp.OP_EXTSWSLI)
+ # 5 - 5
+ yield from send(5, 5, MicrOp.OP_CMP, rc=1)
def consumer():
# receive and check results, interspersed with wait states
yield
# 5 + 3 = 8
result = yield from receive()
- assert (result == 8)
+ assert result[0] == 8
# 2 * 3 = 6
+ # 6 > 0 => CR = 0b100
result = yield from receive()
- assert (result == 6)
+ assert result == (6, 0b100)
yield
yield
- # (-5) + 3 = -2
+ # (-6) + 3 = -3
+ # -3 < 0 => CR = 0b010
result = yield from receive()
- assert (result == 65533) # unsigned equivalent to -2
+ assert result == (65533, 0b010) # unsigned equivalent to -2
# 5 - 3 = 2
# note that this is a zero-delay operation
# this, and the previous result, will be received back-to-back
# (check the output waveform to see this)
result = yield from receive()
- assert (result == 2)
+ assert result[0] == 2
yield
yield
+ # NOP
+ yield from receive()
# 13 >> 2 = 3
result = yield from receive()
- assert (result == 3)
+ assert result[0] == 3
# sign extent 13 = 13
result = yield from receive()
- assert (result == 13)
+ assert result[0] == 13
# sign extend -128 (8 bits) = -128 (16 bits)
+ # -128 < 0 => CR = 0b010
result = yield from receive()
- assert (result == 0xFF80)
+ assert result == (0xFF80, 0b010)
# sign extend -128 (8 bits) = -128 (16 bits)
result = yield from receive()
- assert (result == 0xFF80)
+ assert result[0] == 0xFF80
+ # 5 - 5 = 0
+ # 0 == 0 => CR = 0b001
+ result = yield from receive()
+ assert result == (0, 0b001)
sim.add_sync_process(producer)
sim.add_sync_process(consumer)
'valid_o',
'ready_i',
'alu_o[15:0]',
+ 'alu_o_ok',
+ 'alu_cr[15:0]',
+ 'alu_cr_ok'
]
# determine the module name of the DUT
module = 'top'
projects / soc.git / blobdiff