Add zero CR test case and fix comments

[soc.git] / src / soc / experiment / alu_hier.py

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index c01cc26ee2d5eb94811cfdd82a47f2f03c04c2a0..7aecaf692910b611333cc2b79480d1130fab6521 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -198,7 +198,7 @@ class ALU(Elaboratable):
         self.a, self.b = i[0], i[1]
         out = []
         out.append(Data(width, name="alu_o"))
-        out.append(Data(3, name="alu_cr"))
+        out.append(Data(width, name="alu_cr"))
         self.out = Array(out)
         self.o = self.out[0]
         self.cr = self.out[1]
@@ -208,6 +208,7 @@ class ALU(Elaboratable):
         self.p.data_i.a = self.a
         self.p.data_i.b = self.b
         self.n.data_o.o = self.o
+        self.n.data_o.cr = self.cr
 
     def elaborate(self, platform):
         m = Module()
@@ -265,12 +266,14 @@ class ALU(Elaboratable):
         # hold the ALU result until ready_o is asserted
         alu_r = Signal(self.width)
 
-        # condition register output enable
-        cr_ok_r = Signal()
-
-        # NOP doesn't output anything
-        with m.If(self.op.insn_type != MicrOp.OP_NOP):
+        # output masks
+        # NOP and ILLEGAL don't output anything
+        with m.If((self.op.insn_type != MicrOp.OP_NOP) &
+                  (self.op.insn_type != MicrOp.OP_ILLEGAL)):
             m.d.comb += self.o.ok.eq(1)
+        # CR is output when rc bit is active
+        m.d.comb += self.cr.ok.eq(self.op.rc.rc)
+
         with m.If(alu_idle):
             with m.If(self.p.valid_i):
 
@@ -308,9 +311,6 @@ class ALU(Elaboratable):
                 with m.Else():
                     m.d.comb += go_now.eq(1)
 
-                # store rc bit, to enable cr output later
-                m.d.sync += cr_ok_r.eq(self.op.rc.rc)
-
         with m.Elif(~alu_done | self.n.ready_i):
             # decrement the counter while the ALU is neither idle nor finished
             m.d.sync += self.counter.eq(self.counter - 1)
@@ -318,20 +318,17 @@ class ALU(Elaboratable):
         # choose between zero-delay output, or registered
         with m.If(go_now):
             m.d.comb += self.o.data.eq(sub.o)
-            m.d.comb += self.cr.ok.eq(self.op.rc.rc)
         # only present the result at the last computation cycle
         with m.Elif(alu_done):
             m.d.comb += self.o.data.eq(alu_r)
-            m.d.comb += self.cr.ok.eq(cr_ok_r)
 
         # determine condition register bits based on the data output value
-        with m.If(self.cr.ok):
-            with m.If(~self.o.data.any()):
-                m.d.comb += self.cr.data.eq(0b001)
-            with m.Elif(self.o.data[-1]):
-                m.d.comb += self.cr.data.eq(0b010)
-            with m.Else():
-                m.d.comb += self.cr.data.eq(0b100)
+        with m.If(~self.o.data.any()):
+            m.d.comb += self.cr.data.eq(0b001)
+        with m.Elif(self.o.data[-1]):
+            m.d.comb += self.cr.data.eq(0b010)
+        with m.Else():
+            m.d.comb += self.cr.data.eq(0b100)
 
         return m
 
@@ -588,6 +585,8 @@ def test_alu_parallel():
         yield from send(0x80, 2, MicrOp.OP_EXTS, rc=1)
         # sign extend -128 (8 bits)
         yield from send(2, 0x80, MicrOp.OP_EXTSWSLI)
+        # 5 - 5
+        yield from send(5, 5, MicrOp.OP_CMP, rc=1)
 
     def consumer():
         # receive and check results, interspersed with wait states
@@ -598,11 +597,13 @@ def test_alu_parallel():
         result = yield from receive()
         assert result[0] == 8
         # 2 * 3 = 6
+        # 6 > 0 => CR = 0b100
         result = yield from receive()
         assert result == (6, 0b100)
         yield
         yield
         # (-6) + 3 = -3
+        # -3 < 0 => CR = 0b010
         result = yield from receive()
         assert result == (65533, 0b010)  # unsigned equivalent to -2
         # 5 - 3 = 2
@@ -622,11 +623,16 @@ def test_alu_parallel():
         result = yield from receive()
         assert result[0] == 13
         # sign extend -128 (8 bits) = -128 (16 bits)
+        # -128 < 0 => CR = 0b010
         result = yield from receive()
         assert result == (0xFF80, 0b010)
         # sign extend -128 (8 bits) = -128 (16 bits)
         result = yield from receive()
         assert result[0] == 0xFF80
+        # 5 - 5 = 0
+        # 0 == 0 => CR = 0b001
+        result = yield from receive()
+        assert result == (0, 0b001)
 
     sim.add_sync_process(producer)
     sim.add_sync_process(consumer)
@@ -650,7 +656,7 @@ def write_alu_gtkw(gtkw_name, clk_period=1e-6, sub_module=None,
         'ready_i',
         'alu_o[15:0]',
         'alu_o_ok',
-        'alu_cr[2:0]',
+        'alu_cr[15:0]',
         'alu_cr_ok'
     ]
     # determine the module name of the DUT