test_ldst_pi.py: add dcache regression and random test from test_dcache.py

[soc.git] / src / soc / experiment / cache_ram.py

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index e139546e15ea34517db5eb8a531101aa797c1c22..50ee1367cc84301bcf9cecf0f6cae51d13273227 100644 (file)
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -1,9 +1,12 @@
 # TODO: replace with Memory at some point
 from nmigen import Elaboratable, Signal, Array, Module
+from nmutil.util import Display
 
 class CacheRam(Elaboratable):
 
-    def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=False, ADD_BUF=False):
+    def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False,
+                       ram_num=0):
+        self.ram_num = ram_num # for debug reporting
         self.ROW_BITS = ROW_BITS
         self.WIDTH = WIDTH
         self.TRACE = TRACE
@@ -17,6 +20,7 @@ class CacheRam(Elaboratable):
  
     def elaborate(self, platform):
         m = Module()
+        comb, sync = m.d.comb, m.d.sync
 
         ROW_BITS = self.ROW_BITS
         WIDTH = self.WIDTH
@@ -29,28 +33,28 @@ class CacheRam(Elaboratable):
      
         rd_data0 = Signal(WIDTH)
      
-        sel0 = Signal(WIDTH//8) # defaults to zero
-
         with m.If(TRACE):
-            with m.If(self.wr_sel != sel0):
-                #Display( "write a:" & to_hstring(wr_addr) &
-                #    " sel:" & to_hstring(wr_sel) &
-                #    " dat:" & to_hstring(wr_data))
-               pass
+            with m.If(self.wr_sel.bool()):
+                sync += Display( "write ramno %d a: %%x "
+                                 "sel: %%x dat: %%x" % self.ram_num,
+                                self.wr_addr,
+                                self.wr_sel, self.wr_data)
         for i in range(WIDTH//8):
             lbit = i * 8;
             mbit = lbit + 8;
             with m.If(self.wr_sel[i]):
-                sync += ram[self.wr_addr][lbit:mbit].eq(wr_data(lbit:mbit]))
+                sync += ram[self.wr_addr][lbit:mbit].eq(self.wr_data[lbit:mbit])
         with m.If(self.rd_en):
-            if ADD_BUF:
-                sync += self.rd_data_o.eq(ram[rd_addr])
-            else:
-                comb += self.rd_data_o.eq(ram[rd_addr])
+            sync += rd_data0.eq(ram[self.rd_addr])
+            if TRACE:
+                sync += Display("read ramno %d a: %%x dat: %%x" % self.ram_num,
+                                self.rd_addr, ram[self.rd_addr])
+                pass
+
 
-        if TRACE:
-            # Display( "read a:" & to_hstring(rd_addr) &
-            #" dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
-            pass
+        if ADD_BUF:
+            sync += self.rd_data_o.eq(rd_data0)
+        else:
+            comb += self.rd_data_o.eq(rd_data0)
 
         return m