test_dcbz_pi.py: dcbz now working

[soc.git] / src / soc / experiment / compalu.py

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index f3952413b1c93347a544b5c5665f290bb97b09fb..05539cd485ac833266595e23a92d7034c90d5d67 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -3,10 +3,10 @@ from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Mux, Elaboratable
 
 from nmutil.latch import SRLatch, latchregister
-from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import InternalOp
+from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MicrOp
 
-from .alu_hier import CompALUOpSubset
+from soc.experiment.alu_hier import CompALUOpSubset
 
 """ Computation Unit (aka "ALU Manager").
 
@@ -98,11 +98,11 @@ class ComputationUnitNoDelay(Elaboratable):
 
         # create a latch/register for the operand
         oper_r = CompALUOpSubset()
-        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
+        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True)  # Dest register
-        latchregister(m, self.alu.o, data_r, req_l.q, "data_r")
+        latchregister(m, self.alu.o, data_r, req_l.q, "data_l")
 
         # pass the operation to the ALU
         m.d.comb += self.alu.op.eq(oper_r)
@@ -175,7 +175,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
     yield dut.src1_i.eq(a)
     yield dut.src2_i.eq(b)
     yield dut.oper_i.insn_type.eq(op)
-    yield dut.oper_i.invert_a.eq(inv_a)
+    yield dut.oper_i.invert_in.eq(inv_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.issue_i.eq(1)
@@ -211,20 +211,20 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
 
 
 def scoreboard_sim(dut):
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
                                imm=8, imm_ok=1)
     assert result == 13
 
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
     assert result == 65532
 
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
     assert result == 7
 
 
 def test_scoreboard():
     from alu_hier import ALU
-    from soc.decoder.power_decoder2 import Decode2ToExecute1Type
+    from openpower.decoder.power_decoder2 import Decode2ToExecute1Type
 
     alu = ALU(16)
     dut = ComputationUnitNoDelay(16, alu)