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[soc.git] / src / soc / experiment / compalu.py

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index 0cc2651519e3da99daf45ed4336c344b3a714e12..89d2da1a2c8c0210b0733d6a9c5b0f2ef634b92c 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -4,7 +4,7 @@ from nmigen import Module, Signal, Mux, Elaboratable
 
 from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 
 from soc.experiment.alu_hier import CompALUOpSubset
 
@@ -98,11 +98,11 @@ class ComputationUnitNoDelay(Elaboratable):
 
         # create a latch/register for the operand
         oper_r = CompALUOpSubset()
-        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
+        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True)  # Dest register
-        latchregister(m, self.alu.o, data_r, req_l.q, "data_r")
+        latchregister(m, self.alu.o, data_r, req_l.q, "data_l")
 
         # pass the operation to the ALU
         m.d.comb += self.alu.op.eq(oper_r)
@@ -175,7 +175,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
     yield dut.src1_i.eq(a)
     yield dut.src2_i.eq(b)
     yield dut.oper_i.insn_type.eq(op)
-    yield dut.oper_i.invert_a.eq(inv_a)
+    yield dut.oper_i.invert_in.eq(inv_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.issue_i.eq(1)
@@ -211,14 +211,14 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
 
 
 def scoreboard_sim(dut):
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
                                imm=8, imm_ok=1)
     assert result == 13
 
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
     assert result == 65532
 
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+    result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
     assert result == 7