test_ldst_pi.py: add dcache regression and random test from test_dcache.py

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index fe1b93c0c46ed404852b83435fe9dcc03dae4a3c..d7e32f28c556e76aff9be146ce280eba9745bb09 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -270,11 +270,14 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
                 # bye-bye abstract interface design..
                 fname = find_ok(data_r.fields)
                 if fname:
-                    ok = data_r[fname]
+                    ok = getattr(lro, fname)
             else:
                 data_r = Signal.like(lro, name=name, reset_less=True)
             wrok.append(ok & self.busy_o)
-            latchregister(m, lro, data_r, alu_pulsem, name + "_l")
+            with m.If(alu_pulse):
+                m.d.sync += data_r.eq(lro)
+            with m.If(self.issue_i):
+                m.d.sync += data_r.eq(0)
             drl.append(data_r)
 
         # ok, above we collated anything with an "ok" on the output side
@@ -305,8 +308,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         if hasattr(op, "imm_data"):
             # select immediate if opcode says so. however also change the latch
             # to trigger *from* the opcode latch instead.
-            op_is_imm = op.imm_data.imm_ok
-            imm = op.imm_data.imm
+            op_is_imm = op.imm_data.ok
+            imm = op.imm_data.data
             self._mux_op(m, sl, op_is_imm, imm, 1)
 
         # create a latch/register for src1/src2 (even if it is a copy of imm)