get compldst.py unit test up and running after modifications to ALU

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 56cdd4f929b029c0b7a7935a45f8cba723181f74..dddb1f7730c1b2f3c467683adb22a6e5299412da 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -56,7 +56,7 @@ class ComputationUnitNoDelay(Elaboratable):
             src.append(Signal(rwid, name="src%d_i" % j, reset_less=True))
 
         dst = []
-        for i in range(n_src):
+        for i in range(n_dst):
             j = i + 1 # name numbering to match dest1/2...
             dst.append(Signal(rwid, name="dest%d_i" % j, reset_less=True))
 
@@ -97,7 +97,7 @@ class ComputationUnitNoDelay(Elaboratable):
         # write_requests all done
         wr_any = Signal(reset_less=True)
         req_done = Signal(reset_less=True)
-        m.d.comb += self.done_o.eq(~(self.req_rel_o.bool()))
+        m.d.comb += self.done_o.eq(self.busy_o & ~(self.req_rel_o.bool()))
         m.d.comb += wr_any.eq(self.go_wr_i.bool())
         m.d.comb += req_done.eq(self.done_o & rst_l.q & wr_any)
 
@@ -231,9 +231,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_rd_i.eq(0b10)
-    yield
-    yield dut.go_rd_i.eq(0b01)
+    yield dut.go_rd_i.eq(0b11)
     while True:
         yield
         rd_rel_o = yield dut.rd_rel_o
@@ -281,11 +279,12 @@ def test_scoreboard():
     alu = ALU(16)
     dut = ComputationUnitNoDelay(16, alu)
     m.submodules.cu = dut
-    run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
 
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_compalu.il", "w") as f:
         f.write(vl)
 
+    run_simulation(m, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
+
 if __name__ == '__main__':
     test_scoreboard()