Remove wait state to demonstrate zero-delay reception.

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 4c1f019170159f6b5d57d40f0a06c67cf3e5375d..e2f8683a16fca02d44b73e68355807a0f7e84a9c 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -77,6 +77,7 @@ class CompUnitRecord(RegSpec, RecordObject):
             j = i + 1 # name numbering to match dest1/2...
             name = "dest%d_o" % j
             rw = self._get_dstwid(i)
+            #dreg = Data(rw, name=name) XXX ??? output needs to be a Data type?
             dreg = Signal(rw, name=name, reset_less=True)
             setattr(self, name, dreg)
             dst.append(dreg)
@@ -100,7 +101,7 @@ class CompUnitRecord(RegSpec, RecordObject):
 
 
 class MultiCompUnit(RegSpecALUAPI, Elaboratable):
-    def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1):
+    def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1, name=None):
         """MultiCompUnit
 
         * :rwid:        width of register latches (TODO: allocate per regspec)
@@ -110,6 +111,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         * :n_dst:       number of destination operands
         """
         RegSpecALUAPI.__init__(self, rwid, alu)
+        self.alu_name = name or "alu"
         self.opsubsetkls = opsubsetkls
         self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst)
         n_src, n_dst = self.n_src, self.n_dst = cu._n_src, cu._n_dst
@@ -149,7 +151,6 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         self.data_o = self.dest[0] # Dest out
         self.done_o = cu.done_o
 
-
     def _mux_op(self, m, sl, op_is_imm, imm, i):
         # select imm if opcode says so. however also change the latch
         # to trigger *from* the opcode latch instead.
@@ -164,7 +165,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.alu = self.alu
+        setattr(m.submodules, self.alu_name, self.alu)
         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
@@ -194,6 +195,11 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += alu_pulse.eq(alu_done & ~alu_done_dly)
         m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
 
+        # sigh bug where req_l gets both set and reset raised at same time
+        prev_wr_go = Signal(self.n_dst)
+        brd = Repl(self.busy_o, self.n_dst)
+        m.d.sync += prev_wr_go.eq(self.wr.go & brd)
+
         # write_requests all done
         # req_done works because any one of the last of the writes
         # is enough, when combined with when read-phase is done (rst_l.q)
@@ -201,7 +207,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         req_done = Signal(reset_less=True)
         m.d.comb += self.done_o.eq(self.busy_o & \
                                    ~((self.wr.rel & ~self.wrmask).bool()))
-        m.d.comb += wr_any.eq(self.wr.go.bool())
+        m.d.comb += wr_any.eq(self.wr.go.bool() | prev_wr_go.bool())
         m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i & \
                 ((req_l.q & self.wrmask) == 0))
         # argh, complicated hack: if there are no regs to write,
@@ -223,7 +229,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 
         # read-done,wr-proceed latch
         m.d.comb += rok_l.s.eq(self.issue_i)  # set up when issue starts
-        m.d.comb += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
+        m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
 
         # wr-done, back-to-start latch
         m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
@@ -238,8 +244,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.sync += src_l.r.eq(reset_r)
 
         # dest operand latch (not using issue_i)
-        m.d.comb += req_l.s.eq(alu_pulsem)
-        m.d.comb += req_l.r.eq(reset_w)
+        m.d.comb += req_l.s.eq(alu_pulsem & self.wrmask)
+        m.d.comb += req_l.r.eq(reset_w | prev_wr_go)
 
         # create a latch/register for the operand
         oper_r = self.opsubsetkls(name="oper_r")