make argv handling more flexible

[soc.git] / src / soc / experiment / compldst_multi.py

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 895f8630a8a633c457c73526c4375025d3c82f34..2baedc29f03cdb4a49431d9b69f21ee8cdd901bb 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -294,6 +294,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         rda_any = Signal(reset_less=True)   # any read for address ops
         rd_done = Signal(reset_less=True)   # all *necessary* operands read
         wr_reset = Signal(reset_less=True)  # final reset condition
+        canceln = Signal(reset_less=True)   # cancel (active low)
 
         # LD and ALU out
         alu_o = Signal(self.data_wid, reset_less=True)
@@ -444,7 +445,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
         comb += alu_o.eq(src1_or_z + src2_or_imm)  # actual EA
-        m.d.sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
+        m.d.sync += alu_ok.eq(alu_valid & canceln) # keep ack in sync with EA
 
         ############################
         # Control Signal calculation
@@ -463,7 +464,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
 
         # alu input valid when 1st and 2nd ops done (or imm not active)
-        comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
+        comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]) &
+                             canceln)
 
         # 3rd operand only needed when operation is a store
         comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
@@ -477,8 +479,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # the write/store (etc) all must be cancelled if an exception occurs
         # note: cancel is active low, like shadown_i,
         #       while exc_o.happpened is active high
-        canceln = Signal(reset_less=True)
-        comb += cancel.eq(~self.exc_o.happened & self.shadown_i)
+        comb += canceln.eq(~self.exc_o.happened & self.shadown_i)
 
         # store release when st ready *and* all operands read (and no shadow)
         # dcbz is special case of store -- TODO verify shadows
@@ -532,13 +533,15 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder
         with m.If(op_is_dcbz):
-            sync += Display("MMUTEST.DCBZ: EA from adder %i",addr_r)
+            sync += Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r)
 
         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
         comb += self.exc_o.eq(pi.exc_o)  # exception occurred
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
         # connect MSR.PR for priv/virt operation
         comb += pi.msr_pr.eq(oper_r.msr[MSR.PR])
+        comb += Display("LDSTCompUnit: oper_r.msr %x pi.msr_pr=%x",
+                                      oper_r.msr, oper_r.msr[MSR.PR])
 
         # byte-reverse on LD
         revnorev = Signal(64, reset_less=True)