-""" LOAD / STORE Computation Unit.
+"""LOAD / STORE Computation Unit.
- This module covers POWER9-compliant Load and Store operations,
- with selection on each between immediate and indexed mode as
- options for the calculation of the Effective Address (EA),
- and also "update" mode which optionally stores that EA into
- an additional register.
+This module covers POWER9-compliant Load and Store operations,
+with selection on each between immediate and indexed mode as
+options for the calculation of the Effective Address (EA),
+and also "update" mode which optionally stores that EA into
+an additional register.
- ----
- Note: it took 15 attempts over several weeks to redraw the diagram
- needed to capture this FSM properly. To understand it fully, please
- take the time to review the links, video, and diagram.
- ----
+----
+Note: it took 15 attempts over several weeks to redraw the diagram
+needed to capture this FSM properly. To understand it fully, please
+take the time to review the links, video, and diagram.
+----
- Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
- compute the "Effective Address", and, when ready the operand (src3_i)
- is stored in the computed address (passed through to the PortInterface)
+Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
+compute the "Effective Address", and, when ready the operand (src3_i)
+is stored in the computed address (passed through to the PortInterface)
- Loads are activated when Go_Write[0] is enabled. The EA is computed,
- and (as long as there was no exception) the data comes out (at any
- time from the PortInterface), and is captured by the LDCompSTUnit.
+Loads are activated when Go_Write[0] is enabled. The EA is computed,
+and (as long as there was no exception) the data comes out (at any
+time from the PortInterface), and is captured by the LDCompSTUnit.
- Both LD and ST may request that the address be computed from summing
- operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
- the immediate (from the opcode).
+Both LD and ST may request that the address be computed from summing
+operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
+the immediate (from the opcode).
- Both LD and ST may also request "update" mode (op_is_update) which
- activates the use of Go_Write[1] to control storage of the EA into
- a *second* operand in the register file.
+Both LD and ST may also request "update" mode (op_is_update) which
+activates the use of Go_Write[1] to control storage of the EA into
+a *second* operand in the register file.
- Thus this module has *TWO* write-requests to the register file and
- *THREE* read-requests to the register file (not all at the same time!)
- The regfile port usage is:
+Thus this module has *TWO* write-requests to the register file and
+*THREE* read-requests to the register file (not all at the same time!)
+The regfile port usage is:
* LD-imm 1R1W
* LD-imm-update 1R2W
* ST-idx 3R
* ST-idx-update 3R1W
- It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
- is not suited to (nmigen.FSM is clock-driven, and some aspects of
- the nested FSMs below are *combinatorial*).
+It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
+is not suited to (nmigen.FSM is clock-driven, and some aspects of
+the nested FSMs below are *combinatorial*).
* One FSM covers Operand collection and communication address-side
with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
* The "overall" (fourth) FSM coordinates the progression and completion
of the three other FSMs, firing "WR_RESET" which switches off "busy"
- Full diagram:
+Full diagram:
+
https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
- Links including to walk-through videos:
+Links including to walk-through videos:
+
* https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
+ * http://libre-soc.org/openpower/isa/fixedload
+ * http://libre-soc.org/openpower/isa/fixedstore
+
+Related Bugreports:
- Related Bugreports:
* https://bugs.libre-soc.org/show_bug.cgi?id=302
+ * https://bugs.libre-soc.org/show_bug.cgi?id=216
- Terminology:
+Terminology:
* EA - Effective Address
* LD - Load
from nmutil.latch import SRLatch, latchregister
-from soc.experiment.compalu_multi import go_record
+from soc.experiment.compalu_multi import go_record, CompUnitRecord
from soc.experiment.l0_cache import PortInterface
from soc.experiment.testmem import TestMemory
-from soc.decoder.power_enums import InternalOp
+from soc.fu.regspec import RegSpecAPI
from soc.decoder.power_enums import InternalOp, Function
+from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
+from soc.decoder.power_decoder2 import Data
-class CompLDSTOpSubset(Record):
- """CompLDSTOpSubset
+class LDSTCompUnitRecord(CompUnitRecord):
+ def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
+ CompUnitRecord.__init__(self, opsubset, rwid,
+ n_src=3, n_dst=2, name=name)
- a copy of the relevant subset information from Decode2Execute1Type
- needed for LD/ST operations. use with eq_from_execute1 (below) to
- grab subsets.
- """
- def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
- ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
- ('is_32bit', 1),
- ('is_signed', 1),
- ('data_len', 4), # TODO: should be in separate CompLDSTSubset
- ('byte_reverse', 1),
- ('sign_extend', 1),
- ('update', 1))
-
- Record.__init__(self, Layout(layout), name=name)
-
- # grrr. Record does not have kwargs
- self.insn_type.reset_less = True
- self.is_32bit.reset_less = True
- self.is_signed.reset_less = True
- self.data_len.reset_less = True
- self.byte_reverse.reset_less = True
- self.sign_extend.reset_less = True
- self.update.reset_less = True
-
- def eq_from_execute1(self, other):
- """ use this to copy in from Decode2Execute1Type
- """
- res = []
- for fname, sig in self.fields.items():
- eqfrom = other.fields[fname]
- res.append(sig.eq(eqfrom))
- return res
+ self.ad = go_record(1, name="ad") # address go in, req out
+ self.st = go_record(1, name="st") # store go in, req out
- def ports(self):
- return [self.insn_type,
- self.is_32bit,
- self.is_signed,
- self.data_len,
- self.byte_reverse,
- self.sign_extend,
- self.update,
- ]
+ self.addr_exc_o = Signal(reset_less=True) # address exception
+
+ self.ld_o = Signal(reset_less=True) # operation is a LD
+ self.st_o = Signal(reset_less=True) # operation is a ST
+
+ # hmm... are these necessary?
+ self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
+ self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
-class LDSTCompUnit(Elaboratable):
+class LDSTCompUnit(RegSpecAPI, Elaboratable):
"""LOAD / STORE Computation Unit
Inputs
depending on whether the operation is a ST or LD.
"""
- def __init__(self, pi, rwid=64, awid=48, debugtest=False):
- self.rwid = rwid
+ def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
+ debugtest=False):
+ super().__init__(rwid)
self.awid = awid
self.pi = pi
+ self.cu = cu = LDSTCompUnitRecord(rwid, opsubset)
self.debugtest = debugtest
# POWER-compliant LD/ST has index and update: *fixed* number of ports
self.n_dst = n_dst = 2 # RA, RT/RS
# set up array of src and dest signals
- src = []
for i in range(n_src):
j = i + 1 # name numbering to match src1/src2
- src.append(Signal(rwid, name="src%d_i" % j, reset_less=True))
+ name = "src%d_i" % j
+ setattr(self, name, getattr(cu, name))
dst = []
for i in range(n_dst):
j = i + 1 # name numbering to match dest1/2...
- dst.append(Signal(rwid, name="dest%d_o" % j, reset_less=True))
-
- # control (dual in/out)
- self.rd = go_record(n_src, name="rd") # read in, req out
- self.wr = go_record(n_dst, name="wr") # write in, req out
- self.ad = go_record(1, name="ad") # address go in, req out
- self.st = go_record(1, name="st") # store go in, req out
+ name = "dest%d_o" % j
+ setattr(self, name, getattr(cu, name))
+
+ # convenience names
+ self.rd = cu.rd
+ self.wr = cu.wr
+ self.rdmaskn = cu.rdmaskn
+ self.wrmask = cu.wrmask
+ self.ad = cu.ad
+ self.st = cu.st
+ self.dest = cu._dest
+
+ # HACK: get data width from dest[0]. this is used across the board
+ # (it really shouldn't be)
+ self.data_wid = self.dest[0].shape()
self.go_rd_i = self.rd.go # temporary naming
self.go_wr_i = self.wr.go # temporary naming
- self.rd_rel_o = self.rd.rel # temporary naming
- self.req_rel_o = self.wr.rel # temporary naming
-
self.go_ad_i = self.ad.go # temp naming: go address in
self.go_st_i = self.st.go # temp naming: go store in
- # control inputs
- self.issue_i = Signal(reset_less=True) # fn issue in
- self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
- self.go_die_i = Signal() # go die (reset)
-
- # operation / data input
- self.oper_i = CompLDSTOpSubset() # operand
- self.src_i = Array(src)
- self.src1_i = src[0] # oper1 in: RA
- self.src2_i = src[1] # oper2 in: RB
- self.src3_i = src[2] # oper2 in: RC (RS)
-
- # outputs
- self.busy_o = Signal(reset_less=True) # fn busy out
- self.done_o = Signal(reset_less=True) # final release signal
- # TODO (see bug #302)
- self.addr_exc_o = Signal(reset_less=True) # address exception
- self.dest = Array(dst)
- self.data_o = dst[0] # Dest1 out: RT
- self.addr_o = dst[1] # Address out (LD or ST) - Update => RA
-
+ self.rd_rel_o = self.rd.rel # temporary naming
+ self.req_rel_o = self.wr.rel # temporary naming
self.adr_rel_o = self.ad.rel # request address (from mem)
self.sto_rel_o = self.st.rel # request store (to mem)
- self.ld_o = Signal(reset_less=True) # operation is a LD
- self.st_o = Signal(reset_less=True) # operation is a ST
+ self.issue_i = cu.issue_i
+ self.shadown_i = cu.shadown_i
+ self.go_die_i = cu.go_die_i
- # hmm... are these necessary?
- self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
- self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
+ self.oper_i = cu.oper_i
+ self.src_i = cu._src_i
+
+ self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
+ self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
+ self.addr_exc_o = cu.addr_exc_o
+ self.done_o = cu.done_o
+ self.busy_o = cu.busy_o
+
+ self.ld_o = cu.ld_o
+ self.st_o = cu.st_o
+
+ self.load_mem_o = cu.load_mem_o
+ self.stwd_mem_o = cu.stwd_mem_o
def elaborate(self, platform):
m = Module()
wr_reset = Signal(reset_less=True) # final reset condition
# LD and ALU out
- alu_o = Signal(self.rwid, reset_less=True)
- ldd_o = Signal(self.rwid, reset_less=True)
-
- # select immediate or src2 reg to add
- src2_or_imm = Signal(self.rwid, reset_less=True)
- src_sel = Signal(reset_less=True)
+ alu_o = Signal(self.data_wid, reset_less=True)
+ ldd_o = Signal(self.data_wid, reset_less=True)
##############################
# reset conditions for latches
sync += src_l.s.eq(Repl(issue_i, self.n_src))
sync += src_l.r.eq(reset_r)
- # alu latch
+ # alu latch. use sync-delay between alu_ok and valid to generate pulse
comb += alu_l.s.eq(reset_i)
- comb += alu_l.r.eq(alu_ok & ~rda_any)
+ comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
# addr latch
comb += adr_l.s.eq(reset_i)
comb += rst_l.r.eq(issue_i)
# create a latch/register for the operand
- oper_r = CompLDSTOpSubset() # Dest register
- latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_r")
+ oper_r = CompLDSTOpSubset(name="oper_r") # Dest register
+ latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
# and for LD
- ldd_r = Signal(self.rwid, reset_less=True) # Dest register
+ ldd_r = Signal(self.data_wid, reset_less=True) # Dest register
latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
# and for each input from the incoming src operands
srl = []
for i in range(self.n_src):
name = "src_r%d" % i
- src_r = Signal(self.rwid, name=name, reset_less=True)
- latchregister(m, self.src_i[i], src_r, src_l.q[i], name)
+ src_r = Signal(self.data_wid, name=name, reset_less=True)
+ latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
srl.append(src_r)
# and one for the output from the ADD (for the EA)
- addr_r = Signal(self.rwid, reset_less=True) # Effective Address Latch
- latchregister(m, alu_o, addr_r, alu_l.qn, "ea_r")
+ addr_r = Signal(self.data_wid, reset_less=True) # Effective Address
+ latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
+
+ # select either zero or src1 if opcode says so
+ op_is_z = oper_r.zero_a
+ src1_or_z = Signal(self.data_wid, reset_less=True)
+ m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
# select either immediate or src2 if opcode says so
op_is_imm = oper_r.imm_data.imm_ok
- src2_or_imm = Signal(self.rwid, reset_less=True)
+ src2_or_imm = Signal(self.data_wid, reset_less=True)
m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
# now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
- sync += alu_o.eq(srl[0] + src2_or_imm) # actual EA
+ sync += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
sync += alu_ok.eq(alu_valid) # keep ack in sync with EA
# decode bits of operand (latched)
busy_o = self.busy_o
comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o) # busy out
- # 1st operand read-request is simple: always need it
- comb += self.rd.rel[0].eq(src_l.q[0] & busy_o)
-
+ # 1st operand read-request only when zero not active
# 2nd operand only needed when immediate is not active
- comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
+ slg = Cat(op_is_z, op_is_imm)
+ bro = Repl(self.busy_o, self.n_src)
+ comb += self.rd.rel.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
# note when the address-related read "go" signals are active
comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
# provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
- comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i & wr_any &
+ comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
(lod_l.qn | op_is_st))
comb += self.done_o.eq(wr_reset)
# Data/Address outputs
# put the LD-output register directly onto the output bus on a go_write
+ comb += self.data_o.data.eq(self.dest[0])
with m.If(self.wr.go[0]):
- comb += self.data_o.eq(ldd_r)
+ comb += self.dest[0].eq(ldd_r)
# "update" mode, put address out on 2nd go-write
+ comb += self.addr_o.data.eq(self.dest[1])
with m.If(op_is_update & self.wr.go[1]):
- comb += self.addr_o.eq(addr_r)
+ comb += self.dest[1].eq(addr_r)
+
+ # need to look like MultiCompUnit: put wrmask out.
+ # XXX may need to make this enable only when write active
+ comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
###########################
# PortInterface connections
comb += pi.op.eq(self.oper_i) # op details (not all needed)
# address
comb += pi.addr.data.eq(addr_r) # EA from adder
- comb += pi.addr.ok.eq(self.ad.go) # "go do address stuff"
+ comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine
# ld - ld gets latched in via lod_l
return m
+ def get_out(self, i):
+ """make LDSTCompUnit look like RegSpecALUAPI"""
+ if i == 0:
+ return self.data_o
+ if i == 1:
+ return self.addr_o
+ #return self.dest[i]
+
def __iter__(self):
yield self.rd.go
yield self.go_ad_i
yield self.adr_rel_o
yield self.sto_rel_o
yield self.wr.rel
- yield self.data_o
- yield self.addr_o
+ yield from self.data_o.ports()
+ yield from self.addr_o.ports()
yield self.load_mem_o
yield self.stwd_mem_o
def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
+ print ("ST", src1, src2, src3, imm, imm_ok, update)
yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
+ yield dut.oper_i.data_len.eq(2) # half-word
yield dut.src1_i.eq(src1)
yield dut.src2_i.eq(src2)
yield dut.src3_i.eq(src3)
return addr
-def load(dut, src1, src2, imm, imm_ok=True, update=False):
+def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
+ print ("LD", src1, src2, imm, imm_ok, update)
yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
+ yield dut.oper_i.data_len.eq(2) # half-word
yield dut.src1_i.eq(src1)
yield dut.src2_i.eq(src2)
+ yield dut.oper_i.zero_a.eq(zero_a)
yield dut.oper_i.imm_data.imm.eq(imm)
yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
yield dut.issue_i.eq(1)
yield
yield dut.issue_i.eq(0)
yield
- if imm_ok:
- yield dut.rd.go.eq(0b01)
- else:
- yield dut.rd.go.eq(0b11)
- yield from wait_for(dut.rd.rel)
- yield dut.rd.go.eq(0)
+ rd = 0b00
+ if not imm_ok:
+ rd |= 0b10
+ if not zero_a:
+ rd |= 0b01
+
+ if rd:
+ yield dut.rd.go.eq(rd)
+ yield from wait_for(dut.rd.rel)
+ yield dut.rd.go.eq(0)
yield from wait_for(dut.adr_rel_o, False, test1st=True)
#yield dut.ad.go.eq(1)
# immediate version
# two STs (different addresses)
- yield from store(dut, 4, 0, 3, 2)
- yield from store(dut, 2, 0, 9, 2)
+ yield from store(dut, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
+ yield from store(dut, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
yield
# two LDs (deliberately LD from the 1st address then 2nd)
data, addr = yield from load(dut, 4, 0, 2)
# update-indexed version
data, addr = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
+ assert data == 0x0003, "returned %x" % data
assert addr == 0x0009, "returned %x" % addr
+ # immediate *and* zero version
+ data, addr = yield from load(dut, 4, 5, 9, imm_ok=True, zero_a=True)
+ assert data == 0x0003, "returned %x" % data
+
+
class TestLDSTCompUnit(LDSTCompUnit):
def __init__(self, rwid):
run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
+class TestLDSTCompUnitRegSpec(LDSTCompUnit):
+
+ def __init__(self):
+ from soc.experiment.l0_cache import TstL0CacheBuffer
+ from soc.fu.ldst.pipe_data import LDSTPipeSpec
+ regspec = LDSTPipeSpec.regspec
+ self.l0 = l0 = TstL0CacheBuffer()
+ pi = l0.l0.dports[0].pi
+ LDSTCompUnit.__init__(self, pi, regspec, 4)
+
+ def elaborate(self, platform):
+ m = LDSTCompUnit.elaborate(self, platform)
+ m.submodules.l0 = self.l0
+ m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
+ return m
+
+
+def test_scoreboard_regspec():
+
+ dut = TestLDSTCompUnitRegSpec()
+ vl = rtlil.convert(dut, ports=dut.ports())
+ with open("test_ldst_comp.il", "w") as f:
+ f.write(vl)
+
+ run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_regspec.vcd')
+
+
if __name__ == '__main__':
+ test_scoreboard_regspec()
test_scoreboard()
projects / soc.git / blobdiff