from nmigen.hdl.rec import Record, Layout
from nmutil.latch import SRLatch, latchregister
+from nmutil.byterev import byte_reverse
from soc.experiment.compalu_multi import go_record, CompUnitRecord
from soc.experiment.l0_cache import PortInterface
-from soc.experiment.testmem import TestMemory
+from soc.fu.regspec import RegSpecAPI
from soc.decoder.power_enums import InternalOp, Function
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
+from soc.decoder.power_decoder2 import Data
class LDSTCompUnitRecord(CompUnitRecord):
self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
-class LDSTCompUnit(Elaboratable):
+class LDSTCompUnit(RegSpecAPI, Elaboratable):
"""LOAD / STORE Computation Unit
Inputs
in a single cycle and the CompUnit set back to doing another op.
This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
depending on whether the operation is a ST or LD.
+
+ Note: LDSTCompUnit takes care of LE/BE normalisation:
+ * LD data is normalised after receipt from the PortInterface
+ * ST data is normalised *prior* to sending onto the PortInterface
+ TODO: use one module for the byte-reverse as it's quite expensive in gates
"""
def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
debugtest=False):
- self.rwid = rwid
+ super().__init__(rwid)
self.awid = awid
self.pi = pi
self.cu = cu = LDSTCompUnitRecord(rwid, opsubset)
# convenience names
self.rd = cu.rd
self.wr = cu.wr
+ self.rdmaskn = cu.rdmaskn
+ self.wrmask = cu.wrmask
self.ad = cu.ad
self.st = cu.st
+ self.dest = cu._dest
+
+ # HACK: get data width from dest[0]. this is used across the board
+ # (it really shouldn't be)
+ self.data_wid = self.dest[0].shape()
self.go_rd_i = self.rd.go # temporary naming
self.go_wr_i = self.wr.go # temporary naming
self.oper_i = cu.oper_i
self.src_i = cu._src_i
- self.dest = cu._dest
- self.data_o = self.dest[0] # Dest1 out: RT
- self.addr_o = self.dest[1] # Address out (LD or ST) - Update => RA
+ self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
+ self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
self.addr_exc_o = cu.addr_exc_o
self.done_o = cu.done_o
self.busy_o = cu.busy_o
self.load_mem_o = cu.load_mem_o
self.stwd_mem_o = cu.stwd_mem_o
- # HACK: get data width from dest[0]. this is used across the board
- # (it really shouldn't be)
- self.data_wid = self.dest[0].shape()
-
def elaborate(self, platform):
m = Module()
comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
comb += reset_a.eq(self.go_ad_i | self.go_die_i)
+ p_st_go = Signal(reset_less=True)
+ sync += p_st_go.eq(self.st.go)
+
##########################
# FSM implemented through sequence of latches. approximately this:
# - opc_l : opcode
# dest operand latch
comb += wri_l.s.eq(issue_i)
- sync += wri_l.r.eq(reset_w)
+ sync += wri_l.r.eq(reset_w | Repl(self.done_o, self.n_dst))
# update-mode operand latch (EA written to reg 2)
sync += upd_l.s.eq(reset_i)
# store latch
comb += sto_l.s.eq(addr_ok & op_is_st)
- comb += sto_l.r.eq(reset_s)
+ comb += sto_l.r.eq(reset_s | p_st_go)
# reset latch
comb += rst_l.s.eq(addr_ok) # start when address is ready
comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o) # busy out
# 1st operand read-request only when zero not active
- comb += self.rd.rel[0].eq(src_l.q[0] & busy_o & ~op_is_z)
-
# 2nd operand only needed when immediate is not active
- comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
+ slg = Cat(op_is_z, op_is_imm)
+ bro = Repl(self.busy_o, self.n_src)
+ comb += self.rd.rel.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
# note when the address-related read "go" signals are active
comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
# address release only if addr ready, but Port must be idle
- comb += self.adr_rel_o.eq(adr_l.q & busy_o)
+ comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
# store release when st ready *and* all operands read (and no shadow)
comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
self.shadown_i)
# request write of LD result. waits until shadow is dropped.
- comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
- self.shadown_i)
+ comb += self.wr.rel[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
+ op_is_ld & self.shadown_i)
# request write of EA result only in update mode
comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
self.shadown_i)
# provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
- comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
+ comb += wr_any.eq(self.st.go | p_st_go | self.wr.go[0] | self.wr.go[1])
comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
(lod_l.qn | op_is_st))
# Data/Address outputs
# put the LD-output register directly onto the output bus on a go_write
+ comb += self.data_o.data.eq(self.dest[0])
with m.If(self.wr.go[0]):
- comb += self.data_o.eq(ldd_r)
+ comb += self.dest[0].eq(ldd_r)
# "update" mode, put address out on 2nd go-write
+ comb += self.addr_o.data.eq(self.dest[1])
with m.If(op_is_update & self.wr.go[1]):
- comb += self.addr_o.eq(addr_r)
+ comb += self.dest[1].eq(addr_r)
+
+ # need to look like MultiCompUnit: put wrmask out.
+ # XXX may need to make this enable only when write active
+ comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
###########################
# PortInterface connections
# connect to LD/ST PortInterface.
comb += pi.is_ld_i.eq(op_is_ld & busy_o) # decoded-LD
comb += pi.is_st_i.eq(op_is_st & busy_o) # decoded-ST
- comb += pi.op.eq(self.oper_i) # op details (not all needed)
+ comb += pi.data_len.eq(self.oper_i.data_len) # data_len
# address
comb += pi.addr.data.eq(addr_r) # EA from adder
- comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
+ comb += pi.addr.ok.eq(alu_ok & (lod_l.q | sto_l.q)) # "do address stuff"
comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine
+
+ # byte-reverse on LD - yes this is inverted
+ with m.If(self.oper_i.byte_reverse):
+ comb += ldd_o.eq(pi.ld.data) # put data out, straight (as BE)
+ with m.Else():
+ # byte-reverse the data based on ld/st width (turn it to LE)
+ data_len = self.oper_i.data_len
+ lddata_r = byte_reverse(m, 'lddata_r', pi.ld.data, data_len)
+ comb += ldd_o.eq(lddata_r) # put reversed- data out
# ld - ld gets latched in via lod_l
- comb += ldd_o.eq(pi.ld.data) # ld data goes into ld reg (above)
comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
+
+ # yes this also looks odd (inverted)
+ with m.If(self.oper_i.byte_reverse):
+ comb += pi.st.data.eq(srl[2]) # 3rd operand latch
+ with m.Else():
+ # byte-reverse the data based on width
+ data_len = self.oper_i.data_len
+ stdata_r = byte_reverse(m, 'stdata_r', srl[2], data_len)
+ comb += pi.st.data.eq(stdata_r)
# store - data goes in based on go_st
- comb += pi.st.data.eq(srl[2]) # 3rd operand latch
comb += pi.st.ok.eq(self.st.go) # go store signals st data valid
return m
+ def get_out(self, i):
+ """make LDSTCompUnit look like RegSpecALUAPI"""
+ if i == 0:
+ return self.data_o
+ if i == 1:
+ return self.addr_o
+ #return self.dest[i]
+
def __iter__(self):
yield self.rd.go
yield self.go_ad_i
yield self.adr_rel_o
yield self.sto_rel_o
yield self.wr.rel
- yield self.data_o
- yield self.addr_o
+ yield from self.data_o.ports()
+ yield from self.addr_o.ports()
yield self.load_mem_o
yield self.stwd_mem_o
break
-def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
+def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
+ byterev=True):
print ("ST", src1, src2, src3, imm, imm_ok, update)
yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
+ yield dut.oper_i.data_len.eq(2) # half-word
+ yield dut.oper_i.byte_reverse.eq(byterev)
yield dut.src1_i.eq(src1)
yield dut.src2_i.eq(src2)
yield dut.src3_i.eq(src3)
yield dut.issue_i.eq(1)
yield
yield dut.issue_i.eq(0)
- yield
+
if imm_ok:
- yield dut.rd.go.eq(0b101)
+ active_rel = 0b101
else:
- yield dut.rd.go.eq(0b111)
- yield from wait_for(dut.rd.rel)
+ active_rel = 0b111
+ # wait for all active rel signals to come up
+ while True:
+ rel = yield dut.rd.rel
+ if rel == active_rel:
+ break
+ yield
+ yield dut.rd.go.eq(active_rel)
+ yield
yield dut.rd.go.eq(0)
yield from wait_for(dut.adr_rel_o, False, test1st=True)
return addr
-def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
+def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
+ byterev=True):
print ("LD", src1, src2, imm, imm_ok, update)
yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
+ yield dut.oper_i.data_len.eq(2) # half-word
+ yield dut.oper_i.byte_reverse.eq(byterev)
yield dut.src1_i.eq(src1)
yield dut.src2_i.eq(src2)
yield dut.oper_i.zero_a.eq(zero_a)
yield
yield dut.issue_i.eq(0)
yield
+
+ # set up read-operand flags
rd = 0b00
- if not imm_ok:
+ if not imm_ok: # no immediate means RB register needs to be read
rd |= 0b10
- if not zero_a:
+ if not zero_a: # no zero-a means RA needs to be read
rd |= 0b01
+ # wait for the operands (RA, RB, or both)
if rd:
yield dut.rd.go.eq(rd)
yield from wait_for(dut.rd.rel)
return data, addr
-def scoreboard_sim(dut):
+def ldst_sim(dut):
###################
# immediate version
yield
# indexed version
- yield from store(dut, 4, 5, 3, 0, imm_ok=False)
- data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
+ yield from store(dut, 9, 5, 3, 0, imm_ok=False)
+ data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
assert data == 0x0003, "returned %x" % data
# update-immediate version
- addr = yield from store(dut, 4, 6, 3, 2, update=True)
- assert addr == 0x0006, "returned %x" % addr
+ addr = yield from store(dut, 9, 6, 3, 2, update=True)
+ assert addr == 0x000b, "returned %x" % addr
# update-indexed version
- data, addr = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
+ data, addr = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
assert data == 0x0003, "returned %x" % data
- assert addr == 0x0009, "returned %x" % addr
+ assert addr == 0x000e, "returned %x" % addr
# immediate *and* zero version
- data, addr = yield from load(dut, 4, 5, 9, imm_ok=True, zero_a=True)
- assert data == 0x0003, "returned %x" % data
+ data, addr = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
+ assert data == 0x0008, "returned %x" % data
class TestLDSTCompUnit(LDSTCompUnit):
with open("test_ldst_comp.il", "w") as f:
f.write(vl)
- run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
+ run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
class TestLDSTCompUnitRegSpec(LDSTCompUnit):
with open("test_ldst_comp.il", "w") as f:
f.write(vl)
- run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_regspec.vcd')
+ run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
if __name__ == '__main__':
projects / soc.git / blobdiff