-""" LOAD / STORE Computation Unit.
+"""LOAD / STORE Computation Unit.
- This module covers POWER9-compliant Load and Store operations,
- with selection on each between immediate and indexed mode as
- options for the calculation of the Effective Address (EA),
- and also "update" mode which optionally stores that EA into
- an additional register.
+This module covers POWER9-compliant Load and Store operations,
+with selection on each between immediate and indexed mode as
+options for the calculation of the Effective Address (EA),
+and also "update" mode which optionally stores that EA into
+an additional register.
- ----
- Note: it took 15 attempts over several weeks to redraw the diagram
- needed to capture this FSM properly. To understand it fully, please
- take the time to review the links, video, and diagram.
- ----
+----
+Note: it took 15 attempts over several weeks to redraw the diagram
+needed to capture this FSM properly. To understand it fully, please
+take the time to review the links, video, and diagram.
+----
- Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
- compute the "Effective Address", and, when ready the operand (src3_i)
- is stored in the computed address (passed through to the PortInterface)
+Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
+compute the "Effective Address", and, when ready the operand (src3_i)
+is stored in the computed address (passed through to the PortInterface)
- Loads are activated when Go_Write[0] is enabled. The EA is computed,
- and (as long as there was no exception) the data comes out (at any
- time from the PortInterface), and is captured by the LDCompSTUnit.
+Loads are activated when Go_Write[0] is enabled. The EA is computed,
+and (as long as there was no exception) the data comes out (at any
+time from the PortInterface), and is captured by the LDCompSTUnit.
- Both LD and ST may request that the address be computed from summing
- operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
- the immediate (from the opcode).
+Both LD and ST may request that the address be computed from summing
+operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
+the immediate (from the opcode).
- Both LD and ST may also request "update" mode (op_is_update) which
- activates the use of Go_Write[1] to control storage of the EA into
- a *second* operand in the register file.
+Both LD and ST may also request "update" mode (op_is_update) which
+activates the use of Go_Write[1] to control storage of the EA into
+a *second* operand in the register file.
- Thus this module has *TWO* write-requests to the register file and
- *THREE* read-requests to the register file (not all at the same time!)
- The regfile port usage is:
+Thus this module has *TWO* write-requests to the register file and
+*THREE* read-requests to the register file (not all at the same time!)
+The regfile port usage is:
* LD-imm 1R1W
* LD-imm-update 1R2W
* ST-idx 3R
* ST-idx-update 3R1W
- It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
- is not suited to (nmigen.FSM is clock-driven, and some aspects of
- the nested FSMs below are *combinatorial*).
+It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
+is not suited to (nmigen.FSM is clock-driven, and some aspects of
+the nested FSMs below are *combinatorial*).
* One FSM covers Operand collection and communication address-side
with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
* The "overall" (fourth) FSM coordinates the progression and completion
of the three other FSMs, firing "WR_RESET" which switches off "busy"
- Full diagram:
+Full diagram:
+
https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
- Links including to walk-through videos:
+Links including to walk-through videos:
+
* https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
* http://libre-soc.org/openpower/isa/fixedload
* http://libre-soc.org/openpower/isa/fixedstore
- Related Bugreports:
+Related Bugreports:
+
* https://bugs.libre-soc.org/show_bug.cgi?id=302
+ * https://bugs.libre-soc.org/show_bug.cgi?id=216
- Terminology:
+Terminology:
* EA - Effective Address
* LD - Load
from soc.experiment.compalu_multi import go_record, CompUnitRecord
from soc.experiment.l0_cache import PortInterface
from soc.experiment.testmem import TestMemory
+from soc.fu.regspec import RegSpecAPI
from soc.decoder.power_enums import InternalOp, Function
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
+from soc.decoder.power_decoder2 import Data
class LDSTCompUnitRecord(CompUnitRecord):
- def __init__(self, rwid, name=None):
- CompUnitRecord.__init__(self, CompLDSTOpSubset, rwid,
+ def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
+ CompUnitRecord.__init__(self, opsubset, rwid,
n_src=3, n_dst=2, name=name)
self.ad = go_record(1, name="ad") # address go in, req out
self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
-class LDSTCompUnit(Elaboratable):
+class LDSTCompUnit(RegSpecAPI, Elaboratable):
"""LOAD / STORE Computation Unit
Inputs
depending on whether the operation is a ST or LD.
"""
- def __init__(self, pi=None, rwid=64, awid=48, debugtest=False):
- self.rwid = rwid
+ def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
+ debugtest=False):
+ super().__init__(rwid)
self.awid = awid
self.pi = pi
- self.cu = cu = LDSTCompUnitRecord(rwid)
+ self.cu = cu = LDSTCompUnitRecord(rwid, opsubset)
self.debugtest = debugtest
# POWER-compliant LD/ST has index and update: *fixed* number of ports
# convenience names
self.rd = cu.rd
self.wr = cu.wr
+ self.rdmaskn = cu.rdmaskn
+ self.wrmask = cu.wrmask
self.ad = cu.ad
self.st = cu.st
+ self.dest = cu._dest
+
+ # HACK: get data width from dest[0]. this is used across the board
+ # (it really shouldn't be)
+ self.data_wid = self.dest[0].shape()
self.go_rd_i = self.rd.go # temporary naming
self.go_wr_i = self.wr.go # temporary naming
self.oper_i = cu.oper_i
self.src_i = cu._src_i
- self.dest = cu._dest
- self.data_o = self.dest[0] # Dest1 out: RT
- self.addr_o = self.dest[1] # Address out (LD or ST) - Update => RA
+ self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
+ self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
self.addr_exc_o = cu.addr_exc_o
self.done_o = cu.done_o
self.busy_o = cu.busy_o
wr_reset = Signal(reset_less=True) # final reset condition
# LD and ALU out
- alu_o = Signal(self.rwid, reset_less=True)
- ldd_o = Signal(self.rwid, reset_less=True)
-
- # XXX TODO ZEROing just lije in ComUnit
-
+ alu_o = Signal(self.data_wid, reset_less=True)
+ ldd_o = Signal(self.data_wid, reset_less=True)
##############################
# reset conditions for latches
latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
# and for LD
- ldd_r = Signal(self.rwid, reset_less=True) # Dest register
+ ldd_r = Signal(self.data_wid, reset_less=True) # Dest register
latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
# and for each input from the incoming src operands
srl = []
for i in range(self.n_src):
name = "src_r%d" % i
- src_r = Signal(self.rwid, name=name, reset_less=True)
+ src_r = Signal(self.data_wid, name=name, reset_less=True)
latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
srl.append(src_r)
# and one for the output from the ADD (for the EA)
- addr_r = Signal(self.rwid, reset_less=True) # Effective Address Latch
+ addr_r = Signal(self.data_wid, reset_less=True) # Effective Address
latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
# select either zero or src1 if opcode says so
op_is_z = oper_r.zero_a
- src1_or_z = Signal(self.rwid, reset_less=True)
+ src1_or_z = Signal(self.data_wid, reset_less=True)
m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
# select either immediate or src2 if opcode says so
op_is_imm = oper_r.imm_data.imm_ok
- src2_or_imm = Signal(self.rwid, reset_less=True)
+ src2_or_imm = Signal(self.data_wid, reset_less=True)
m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
# now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o) # busy out
# 1st operand read-request only when zero not active
- comb += self.rd.rel[0].eq(src_l.q[0] & busy_o & ~op_is_z)
-
# 2nd operand only needed when immediate is not active
- comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
+ slg = Cat(op_is_z, op_is_imm)
+ bro = Repl(self.busy_o, self.n_src)
+ comb += self.rd.rel.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
# note when the address-related read "go" signals are active
comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
# Data/Address outputs
# put the LD-output register directly onto the output bus on a go_write
+ comb += self.data_o.data.eq(self.dest[0])
with m.If(self.wr.go[0]):
- comb += self.data_o.eq(ldd_r)
+ comb += self.dest[0].eq(ldd_r)
# "update" mode, put address out on 2nd go-write
+ comb += self.addr_o.data.eq(self.dest[1])
with m.If(op_is_update & self.wr.go[1]):
- comb += self.addr_o.eq(addr_r)
+ comb += self.dest[1].eq(addr_r)
+
+ # need to look like MultiCompUnit: put wrmask out
+ comb += self.wrmask.eq(self.wr.rel)
###########################
# PortInterface connections
return m
+ def get_out(self, i):
+ """make LDSTCompUnit look like RegSpecALUAPI"""
+ if i == 0:
+ return self.data_o
+ if i == 1:
+ return self.addr_o
+ #return self.dest[i]
+
def __iter__(self):
yield self.rd.go
yield self.go_ad_i
run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
+class TestLDSTCompUnitRegSpec(LDSTCompUnit):
+
+ def __init__(self):
+ from soc.experiment.l0_cache import TstL0CacheBuffer
+ from soc.fu.ldst.pipe_data import LDSTPipeSpec
+ regspec = LDSTPipeSpec.regspec
+ self.l0 = l0 = TstL0CacheBuffer()
+ pi = l0.l0.dports[0].pi
+ LDSTCompUnit.__init__(self, pi, regspec, 4)
+
+ def elaborate(self, platform):
+ m = LDSTCompUnit.elaborate(self, platform)
+ m.submodules.l0 = self.l0
+ m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
+ return m
+
+
+def test_scoreboard_regspec():
+
+ dut = TestLDSTCompUnitRegSpec()
+ vl = rtlil.convert(dut, ports=dut.ports())
+ with open("test_ldst_comp.il", "w") as f:
+ f.write(vl)
+
+ run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_regspec.vcd')
+
+
if __name__ == '__main__':
+ test_scoreboard_regspec()
test_scoreboard()
projects / soc.git / blobdiff