and (as long as there was no exception) the data comes out (at any
time from the PortInterface), and is captured by the LDCompSTUnit.
+TODO: dcbz, yes, that's going to be complicated, has to be done
+ with great care, to detect the case when dcbz is set
+ and *not* expect to read any data, just the address.
+ so, wait for RA but not RB.
+
Both LD and ST may request that the address be computed from summing
operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
the immediate (from the opcode).
* A third FSM activates to cover ST. it activates if op_is_st is true
+ * TODO document DCBZ (not complete yet)
+
* The "overall" (fourth) FSM coordinates the progression and completion
of the three other FSMs, firing "WR_RESET" which switches off "busy"
from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
from openpower.decoder.power_decoder2 import Data
+from openpower.consts import MSR
+from soc.config.test.test_loadstore import TestMemPspec
+
+# for debugging dcbz
+from nmutil.util import Display
+
+
+# TODO: LDSTInputData and LDSTOutputData really should be used
+# here, to make things more like the other CompUnits. currently,
+# also, RegSpecAPI is used explicitly here
class LDSTCompUnitRecord(CompUnitRecord):
self.ad = go_record(1, name="cu_ad") # address go in, req out
self.st = go_record(1, name="cu_st") # store go in, req out
- self.exception_o = LDSTException("exc")
+ self.exc_o = LDSTException("exc_o")
self.ld_o = Signal(reset_less=True) # operation is a LD
self.st_o = Signal(reset_less=True) # operation is a ST
Data (outputs)
--------------
- * :data_o: Dest out (LD) - managed by wr[0] go/req
- * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
- * :exception_o: Address/Data Exception occurred. LD/ST must terminate
+ * :o_data: Dest out (LD) - managed by wr[0] go/req
+ * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
+ * :exc_o: Address/Data Exception occurred. LD/ST must terminate
- TODO: make exception_o a data-type rather than a single-bit signal
+ TODO: make exc_o a data-type rather than a single-bit signal
(see bug #302)
Control Signals (In)
self.oper_i = cu.oper_i
self.src_i = cu._src_i
- self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
+ self.o_data = Data(self.data_wid, name="o") # Dest1 out: RT
self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
- self.exception_o = cu.exception_o
+ self.exc_o = cu.exc_o
self.done_o = cu.done_o
self.busy_o = cu.busy_o
# opcode decode
op_is_ld = Signal(reset_less=True)
op_is_st = Signal(reset_less=True)
+ op_is_dcbz = Signal(reset_less=True)
# ALU/LD data output control
alu_valid = Signal(reset_less=True) # ALU operands are valid
reset_r = Signal(self.n_src, reset_less=True) # reset src
reset_s = Signal(reset_less=True) # reset store
- comb += reset_i.eq(issue_i | self.go_die_i) # various
- comb += reset_o.eq(self.done_o | self.go_die_i) # opcode reset
- comb += reset_w.eq(self.wr.go_i[0] | self.go_die_i) # write reg 1
- comb += reset_u.eq(self.wr.go_i[1] | self.go_die_i) # update (reg 2)
- comb += reset_s.eq(self.go_st_i | self.go_die_i) # store reset
- comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
- comb += reset_a.eq(self.go_ad_i | self.go_die_i)
+ # end execution when a terminating condition is detected:
+ # - go_die_i: a speculative operation was cancelled
+ # - exc_o.happened: an exception has occurred
+ terminate = Signal()
+ comb += terminate.eq(self.go_die_i | self.exc_o.happened)
+
+ comb += reset_i.eq(issue_i | terminate) # various
+ comb += reset_o.eq(self.done_o | terminate) # opcode reset
+ comb += reset_w.eq(self.wr.go_i[0] | terminate) # write reg 1
+ comb += reset_u.eq(self.wr.go_i[1] | terminate) # update (reg 2)
+ comb += reset_s.eq(self.go_st_i | terminate) # store reset
+ comb += reset_r.eq(self.rd.go_i | Repl(terminate, self.n_src))
+ comb += reset_a.eq(self.go_ad_i | terminate)
p_st_go = Signal(reset_less=True)
sync += p_st_go.eq(self.st.go_i)
# decode bits of operand (latched)
oper_r = CompLDSTOpSubset(name="oper_r") # Dest register
- comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
- comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
+ comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
+ comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
+ comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ) # DCBZ
+ #uncomment if needed
+ #comb += Display("compldst_multi: op_is_dcbz = %i",
+ # (oper_r.insn_type == MicrOp.OP_DCBZ))
op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE
op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit
comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
# create a latch/register for the operand
with m.If(self.issue_i):
sync += oper_r.eq(self.oper_i)
- with m.If(self.done_o):
+ with m.If(self.done_o | terminate):
sync += oper_r.eq(0)
# and for LD
# address release only if addr ready, but Port must be idle
comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
+ # the write/store (etc) all must be cancelled if an exception occurs
+ # note: cancel is active low, like shadown_i,
+ # while exc_o.happpened is active high
+ cancel = Signal(reset_less=True)
+ comb += cancel.eq(~self.exc_o.happened & self.shadown_i)
+
# store release when st ready *and* all operands read (and no shadow)
comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
- self.shadown_i)
+ cancel)
# request write of LD result. waits until shadow is dropped.
comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
- op_is_ld & self.shadown_i)
+ op_is_ld & cancel)
# request write of EA result only in update mode
comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
- alu_valid & self.shadown_i)
+ alu_valid & cancel)
# provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
comb += wr_any.eq(self.st.go_i | p_st_go |
self.wr.go_i[0] | self.wr.go_i[1])
- comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
+ comb += wr_reset.eq(rst_l.q & busy_o & cancel &
~(self.st.rel_o | self.wr.rel_o[0] |
self.wr.rel_o[1]) &
(lod_l.qn | op_is_st)
# Data/Address outputs
# put the LD-output register directly onto the output bus on a go_write
- comb += self.data_o.data.eq(self.dest[0])
+ comb += self.o_data.data.eq(self.dest[0])
with m.If(self.wr.go_i[0]):
comb += self.dest[0].eq(ldd_r)
# connect to LD/ST PortInterface.
comb += pi.is_ld_i.eq(op_is_ld & busy_o) # decoded-LD
comb += pi.is_st_i.eq(op_is_st & busy_o) # decoded-ST
+ comb += pi.is_dcbz_i.eq(op_is_dcbz & busy_o) # decoded-DCBZ
comb += pi.data_len.eq(oper_r.data_len) # data_len
# address: use sync to avoid long latency
sync += pi.addr.data.eq(addr_r) # EA from adder
+ sync += Display("EA from adder %i op_is_dcbz %i",addr_r,op_is_dcbz)
+ ## do not use ### sync += pi.is_dcbz.eq(op_is_dcbz) # set dcbz
+
sync += pi.addr.ok.eq(alu_ok & lsd_l.q) # "do address stuff" (once)
- comb += self.exception_o.eq(pi.exception_o) # exception occurred
+ comb += self.exc_o.eq(pi.exc_o) # exception occurred
comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine
+ # connect MSR.PR for priv/virt operation
+ comb += pi.msr_pr.eq(oper_r.msr[MSR.PR])
# byte-reverse on LD
revnorev = Signal(64, reset_less=True)
return m
def get_out(self, i):
- """make LDSTCompUnit look like RegSpecALUAPI"""
+ """make LDSTCompUnit look like RegSpecALUAPI. these correspond
+ to LDSTOutputData o and o1 respectively.
+ """
if i == 0:
- return self.data_o
+ return self.o_data # LDSTOutputData.regspec o
if i == 1:
- return self.addr_o
+ return self.addr_o # LDSTOutputData.regspec o1
# return self.dest[i]
def get_fu_out(self, i):
yield self.adr_rel_o
yield self.sto_rel_o
yield self.wr.rel_o
- yield from self.data_o.ports()
+ yield from self.o_data.ports()
yield from self.addr_o.ports()
yield self.load_mem_o
yield self.stwd_mem_o
yield dut.src1_i.eq(src1)
yield dut.src2_i.eq(src2)
yield dut.src3_i.eq(src3)
- yield dut.oper_i.imm_data.imm.eq(imm)
+ yield dut.oper_i.imm_data.data.eq(imm)
yield dut.oper_i.imm_data.ok.eq(imm_ok)
- yield dut.oper_i.update.eq(update)
+ #guess: this one was removed -- yield dut.oper_i.update.eq(update)
yield dut.issue_i.eq(1)
yield
yield dut.issue_i.eq(0)
if rel == active_rel:
break
yield
- yield dut.rd.go.eq(active_rel)
+ yield dut.rd.go_i.eq(active_rel)
yield
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
yield from wait_for(dut.adr_rel_o, False, test1st=True)
# yield from wait_for(dut.adr_rel_o)
yield dut.src1_i.eq(src1)
yield dut.src2_i.eq(src2)
yield dut.oper_i.zero_a.eq(zero_a)
- yield dut.oper_i.imm_data.imm.eq(imm)
+ yield dut.oper_i.imm_data.data.eq(imm)
yield dut.oper_i.imm_data.ok.eq(imm_ok)
yield dut.issue_i.eq(1)
yield
# wait for the operands (RA, RB, or both)
if rd:
- yield dut.rd.go.eq(rd)
+ yield dut.rd.go_i.eq(rd)
yield from wait_for(dut.rd.rel_o)
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
yield from wait_for(dut.adr_rel_o, False, test1st=True)
# yield dut.ad.go.eq(1)
if update:
yield from wait_for(dut.wr.rel_o[1])
- yield dut.wr.go.eq(0b10)
+ yield dut.wr.go_i.eq(0b10)
yield
addr = yield dut.addr_o
print("addr", addr)
- yield dut.wr.go.eq(0)
+ yield dut.wr.go_i.eq(0)
else:
addr = None
yield from wait_for(dut.wr.rel_o[0], test1st=True)
- yield dut.wr.go.eq(1)
+ yield dut.wr.go_i.eq(1)
yield
- data = yield dut.data_o
- print(data)
- yield dut.wr.go.eq(0)
+ data = yield dut.o_data.o
+ data_ok = yield dut.o_data.o_ok
+ yield dut.wr.go_i.eq(0)
yield from wait_for(dut.busy_o)
yield
# wait_for(dut.stwd_mem_o)
- return data, addr
+ return data, data_ok, addr
def ldst_sim(dut):
class TestLDSTCompUnit(LDSTCompUnit):
- def __init__(self, rwid):
+ def __init__(self, rwid, pspec):
from soc.experiment.l0_cache import TstL0CacheBuffer
- self.l0 = l0 = TstL0CacheBuffer()
- pi = l0.l0.dports[0].pi
+ self.l0 = l0 = TstL0CacheBuffer(pspec)
+ pi = l0.l0.dports[0]
LDSTCompUnit.__init__(self, pi, rwid, 4)
def elaborate(self, platform):
m = LDSTCompUnit.elaborate(self, platform)
m.submodules.l0 = self.l0
- m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
+ # link addr-go direct to rel
+ m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
return m
def test_scoreboard():
- dut = TestLDSTCompUnit(16)
+ units = {}
+ pspec = TestMemPspec(ldst_ifacetype='bare_wb',
+ imem_ifacetype='bare_wb',
+ addr_wid=48,
+ mask_wid=8,
+ reg_wid=64,
+ units=units)
+
+ dut = TestLDSTCompUnit(16,pspec)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_ldst_comp.il", "w") as f:
f.write(vl)
class TestLDSTCompUnitRegSpec(LDSTCompUnit):
- def __init__(self):
+ def __init__(self, pspec):
from soc.experiment.l0_cache import TstL0CacheBuffer
from soc.fu.ldst.pipe_data import LDSTPipeSpec
regspec = LDSTPipeSpec.regspec
- self.l0 = l0 = TstL0CacheBuffer()
- pi = l0.l0.dports[0].pi
+ self.l0 = l0 = TstL0CacheBuffer(pspec)
+ pi = l0.l0.dports[0]
LDSTCompUnit.__init__(self, pi, regspec, 4)
def elaborate(self, platform):
m = LDSTCompUnit.elaborate(self, platform)
m.submodules.l0 = self.l0
- m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
+ # link addr-go direct to rel
+ m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
return m
def test_scoreboard_regspec():
- dut = TestLDSTCompUnitRegSpec()
+ units = {}
+ pspec = TestMemPspec(ldst_ifacetype='bare_wb',
+ imem_ifacetype='bare_wb',
+ addr_wid=48,
+ mask_wid=8,
+ reg_wid=64,
+ units=units)
+
+ dut = TestLDSTCompUnitRegSpec(pspec)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_ldst_comp.il", "w") as f:
f.write(vl)
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