from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
from openpower.decoder.power_decoder2 import Data
from openpower.consts import MSR
+from openpower.power_enums import MSRSpec
from soc.config.test.test_loadstore import TestMemPspec
# for debugging dcbz
self.awid = awid
self.pi = pi
self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
- self.debugtest = debugtest
+ self.debugtest = debugtest # enable debug output for unit testing
# POWER-compliant LD/ST has index and update: *fixed* number of ports
self.n_src = n_src = 3 # RA, RB, RT/RS
op_is_ld = Signal(reset_less=True)
op_is_st = Signal(reset_less=True)
op_is_dcbz = Signal(reset_less=True)
+ op_is_st_or_dcbz = Signal(reset_less=True)
# ALU/LD data output control
alu_valid = Signal(reset_less=True) # ALU operands are valid
rda_any = Signal(reset_less=True) # any read for address ops
rd_done = Signal(reset_less=True) # all *necessary* operands read
wr_reset = Signal(reset_less=True) # final reset condition
+ canceln = Signal(reset_less=True) # cancel (active low)
# LD and ALU out
alu_o = Signal(self.data_wid, reset_less=True)
comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ) # DCBZ
+ comb += op_is_st_or_dcbz.eq(op_is_st | op_is_dcbz)
+ # dcbz is special case of store
#uncomment if needed
#comb += Display("compldst_multi: op_is_dcbz = %i",
# (oper_r.insn_type == MicrOp.OP_DCBZ))
sync += opc_l.r.eq(reset_o) # XXX NOTE: INVERTED FROM book!
# src operand latch
- sync += src_l.s.eq(Repl(issue_i, self.n_src))
+ sync += src_l.s.eq(Repl(issue_i, self.n_src) & ~self.rdmaskn)
sync += src_l.r.eq(reset_r)
+ #### sync += Display("reset_r = %i",reset_r)
# alu latch. use sync-delay between alu_ok and valid to generate pulse
comb += alu_l.s.eq(reset_i)
sync += upd_l.r.eq(reset_u)
# store latch
- comb += sto_l.s.eq(addr_ok & op_is_st)
+ comb += sto_l.s.eq(addr_ok & op_is_st_or_dcbz)
sync += sto_l.r.eq(reset_s | p_st_go)
# ld/st done. needed to stop LD/ST from activating repeatedly
# now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
comb += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
- m.d.sync += alu_ok.eq(alu_valid) # keep ack in sync with EA
+ m.d.sync += alu_ok.eq(alu_valid & canceln) # keep ack in sync with EA
############################
# Control Signal calculation
# 1st operand read-request only when zero not active
# 2nd operand only needed when immediate is not active
- slg = Cat(op_is_z, op_is_imm)
+ slg = Cat(op_is_z, op_is_imm) #is this correct ?
bro = Repl(self.busy_o, self.n_src)
- comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
+ comb += self.rd.rel_o.eq(src_l.q & bro & ~slg)
# note when the address-related read "go" signals are active
comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
# alu input valid when 1st and 2nd ops done (or imm not active)
- comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
+ comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]) &
+ canceln)
# 3rd operand only needed when operation is a store
comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
# the write/store (etc) all must be cancelled if an exception occurs
# note: cancel is active low, like shadown_i,
# while exc_o.happpened is active high
- cancel = Signal(reset_less=True)
- comb += cancel.eq(~self.exc_o.happened & self.shadown_i)
+ comb += canceln.eq(~self.exc_o.happened & self.shadown_i)
# store release when st ready *and* all operands read (and no shadow)
- comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
- cancel)
+ # dcbz is special case of store -- TODO verify shadows
+ comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st_or_dcbz &
+ canceln)
# request write of LD result. waits until shadow is dropped.
comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
- op_is_ld & cancel)
+ op_is_ld & canceln)
# request write of EA result only in update mode
comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
- alu_valid & cancel)
+ alu_valid & canceln)
# provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
comb += wr_any.eq(self.st.go_i | p_st_go |
self.wr.go_i[0] | self.wr.go_i[1])
- comb += wr_reset.eq(rst_l.q & busy_o & cancel &
+ comb += wr_reset.eq(rst_l.q & busy_o & canceln &
~(self.st.rel_o | self.wr.rel_o[0] |
self.wr.rel_o[1]) &
- (lod_l.qn | op_is_st)
+ (lod_l.qn | op_is_st_or_dcbz)
)
comb += self.done_o.eq(wr_reset & (~self.pi.busy_o | op_is_ld))
# connect to LD/ST PortInterface.
comb += pi.is_ld_i.eq(op_is_ld & busy_o) # decoded-LD
- comb += pi.is_st_i.eq(op_is_st & busy_o) # decoded-ST
+ comb += pi.is_st_i.eq(op_is_st_or_dcbz & busy_o) # decoded-ST
comb += pi.is_dcbz_i.eq(op_is_dcbz & busy_o) # decoded-DCBZ
comb += pi.data_len.eq(oper_r.data_len) # data_len
# address: use sync to avoid long latency
sync += pi.addr.data.eq(addr_r) # EA from adder
- sync += Display("EA from adder %i op_is_dcbz %i",addr_r,op_is_dcbz)
- ## do not use ### sync += pi.is_dcbz.eq(op_is_dcbz) # set dcbz
+ with m.If(op_is_dcbz):
+ sync += Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r)
sync += pi.addr.ok.eq(alu_ok & lsd_l.q) # "do address stuff" (once)
comb += self.exc_o.eq(pi.exc_o) # exception occurred
comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine
# connect MSR.PR for priv/virt operation
- comb += pi.msr_pr.eq(oper_r.msr[MSR.PR])
+ comb += pi.priv_mode.eq(oper_r.msr[MSR.PR])
+ comb += Display("LDSTCompUnit: oper_r.msr %x pi.msr_pr=%x",
+ oper_r.msr, oper_r.msr[MSR.PR])
# byte-reverse on LD
revnorev = Signal(64, reset_less=True)
if update:
yield from wait_for(dut.wr.rel_o[1])
- yield dut.wr.go.eq(0b10)
+ yield dut.wr.go_i.eq(0b10)
yield
addr = yield dut.addr_o
print("addr", addr)
- yield dut.wr.go.eq(0)
+ yield dut.wr.go_i.eq(0)
else:
addr = None
yield from wait_for(dut.wr.rel_o[0], test1st=True)
- yield dut.wr.go.eq(1)
+ yield dut.wr.go_i.eq(1)
yield
- data = yield dut.o_data
- print(data)
- yield dut.wr.go.eq(0)
+ data = yield dut.o_data.o
+ data_ok = yield dut.o_data.o_ok
+ yield dut.wr.go_i.eq(0)
yield from wait_for(dut.busy_o)
yield
# wait_for(dut.stwd_mem_o)
- return data, addr
+ return data, data_ok, addr
def ldst_sim(dut):
projects / soc.git / blobdiff