from enum import Enum, unique
from nmigen import Module, Signal, Elaboratable, Cat, Repl, Array, Const
-try:
- from nmigen.hdl.ast import Display
-except ImportError:
- def Display(*args):
- return []
+from nmutil.util import Display
+
+from random import randint
from nmigen.cli import main
from nmutil.iocontrol import RecordObject
-from nmutil.util import wrap
from nmigen.utils import log2_int
from soc.experiment.mem_types import (LoadStore1ToDCacheType,
DCacheToLoadStore1Type,
from nmigen.back.pysim import Simulator, Delay, Settle
else:
from nmigen.sim.cxxsim import Simulator, Delay, Settle
+from nmutil.util import wrap
# TODO: make these parameters of DCache at some point
# to represent the full dcache
BRAM_ROWS = NUM_LINES * ROW_PER_LINE
+print ("ROW_SIZE", ROW_SIZE)
+print ("ROW_PER_LINE", ROW_PER_LINE)
+print ("BRAM_ROWS", BRAM_ROWS)
+print ("NUM_WAYS", NUM_WAYS)
# Bit fields counts in the address
WAY_BITS = log2_int(NUM_WAYS)
# Example of layout for 32 lines of 64 bytes:
-#
-# .. tag |index| line |
-# .. | row | |
-# .. | |---| | ROW_LINE_BITS (3)
-# .. | |--- - --| LINE_OFF_BITS (6)
-# .. | |- --| ROW_OFF_BITS (3)
-# .. |----- ---| | ROW_BITS (8)
-# .. |-----| | INDEX_BITS (5)
-# .. --------| | TAG_BITS (45)
+layout = """\
+ .. tag |index| line |
+ .. | row | |
+ .. | |---| | ROW_LINE_BITS (3)
+ .. | |--- - --| LINE_OFF_BITS (6)
+ .. | |- --| ROW_OFF_BITS (3)
+ .. |----- ---| | ROW_BITS (8)
+ .. |-----| | INDEX_BITS (5)
+ .. --------| | TAG_BITS (45)
+"""
+print (layout)
+print ("Dcache TAG %d IDX %d ROW %d ROFF %d LOFF %d RLB %d" % \
+ (TAG_BITS, INDEX_BITS, ROW_BITS,
+ ROW_OFF_BITS, LINE_OFF_BITS, ROW_LINE_BITS))
+print ("index @: %d-%d" % (LINE_OFF_BITS, SET_SIZE_BITS))
+print ("row @: %d-%d" % (LINE_OFF_BITS, ROW_OFF_BITS))
+print ("tag @: %d-%d width %d" % (SET_SIZE_BITS, REAL_ADDR_BITS, TAG_WIDTH))
TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS
def CacheTagArray():
- return Array(Signal(TAG_RAM_WIDTH) for x in range(NUM_LINES))
+ return Array(Signal(TAG_RAM_WIDTH, name="cachetag_%d" % x) \
+ for x in range(NUM_LINES))
def CacheValidBitsArray():
- return Array(Signal(INDEX_BITS) for x in range(NUM_LINES))
+ return Array(Signal(NUM_WAYS, name="cachevalid_%d" % x) \
+ for x in range(NUM_LINES))
def RowPerLineValidArray():
- return Array(Signal(name="rows_valid%d" % x) for x in range(ROW_PER_LINE))
+ return Array(Signal(name="rows_valid%d" % x) \
+ for x in range(ROW_PER_LINE))
# L1 TLB
TLB_SET_BITS = log2_int(TLB_SET_SIZE)
TLB_PTE_BITS = 64
TLB_PTE_WAY_BITS = TLB_NUM_WAYS * TLB_PTE_BITS;
+def ispow2(x):
+ return (1<<log2_int(x, False)) == x
+
assert (LINE_SIZE % ROW_SIZE) == 0, "LINE_SIZE not multiple of ROW_SIZE"
-assert (LINE_SIZE % 2) == 0, "LINE_SIZE not power of 2"
-assert (NUM_LINES % 2) == 0, "NUM_LINES not power of 2"
-assert (ROW_PER_LINE % 2) == 0, "ROW_PER_LINE not power of 2"
+assert ispow2(LINE_SIZE), "LINE_SIZE not power of 2"
+assert ispow2(NUM_LINES), "NUM_LINES not power of 2"
+assert ispow2(ROW_PER_LINE), "ROW_PER_LINE not power of 2"
assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS), "geometry bits don't add up"
assert (LINE_OFF_BITS == ROW_OFF_BITS + ROW_LINE_BITS), \
"geometry bits don't add up"
return Array(Signal(TLB_PTE_WAY_BITS) for x in range(TLB_SET_SIZE))
def HitWaySet():
- return Array(Signal(WAY_BITS) for x in range(TLB_NUM_WAYS))
+ return Array(Signal(WAY_BITS, name="hitway_%d" % x) \
+ for x in range(TLB_NUM_WAYS))
# Cache RAM interface
def CacheRamOut():
- return Array(Signal(WB_DATA_BITS) for x in range(NUM_WAYS))
+ return Array(Signal(WB_DATA_BITS, name="cache_out%d" % x) \
+ for x in range(NUM_WAYS))
# PLRU output interface
def PLRUOut():
# Return the index of a row within a line
def get_row_of_line(row):
- return row[:ROW_LINE_BITS]
+ return row[:ROW_BITS][:ROW_LINE_BITS]
# Returns whether this is the last row of a line
def is_last_row_addr(addr, last):
self.write_bram = Signal()
self.write_tag = Signal()
self.slow_valid = Signal()
- self.wb = WBMasterOut()
+ self.real_adr = Signal(REAL_ADDR_BITS)
+ self.wb = WBMasterOut("wb")
self.reload_tag = Signal(TAG_BITS)
self.store_way = Signal(WAY_BITS)
self.store_row = Signal(ROW_BITS)
return m
- def dcache_request(self, m, r0, ra, req_index, req_row, req_tag,
- r0_valid, r1, cache_valid_bits, replace_way,
- use_forward1_next, use_forward2_next,
- req_hit_way, plru_victim, rc_ok, perm_attr,
- valid_ra, perm_ok, access_ok, req_op, req_go,
- tlb_pte_way,
- tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
- cancel_store, req_same_tag, r0_stall, early_req_row):
- """Cache request parsing and hit detection
- """
class DCachePendingHit(Elaboratable):
req_index = self.req_index
reload_tag = self.reload_tag
- rel_matches = Array(Signal() for i in range(TLB_NUM_WAYS))
+ rel_matches = Array(Signal(name="rel_matches_%d" % i) \
+ for i in range(TLB_NUM_WAYS))
hit_way_set = HitWaySet()
# Test if pending request is a hit on any way
r = RegStage0("stage0")
# TODO, this goes in unit tests and formal proofs
- with m.If(~(d_in.valid & m_in.valid)):
- #sync += Display("request collision loadstore vs MMU")
- pass
+ with m.If(d_in.valid & m_in.valid):
+ sync += Display("request collision loadstore vs MMU")
with m.If(m_in.valid):
sync += r.req.valid.eq(1)
sync += cache_tag_set.eq(cache_tags[index])
def dcache_request(self, m, r0, ra, req_index, req_row, req_tag,
- r0_valid, r1, cache_valid_bits, replace_way,
+ r0_valid, r1, cache_valids, replace_way,
use_forward1_next, use_forward2_next,
req_hit_way, plru_victim, rc_ok, perm_attr,
valid_ra, perm_ok, access_ok, req_op, req_go,
opsel = Signal(3)
go = Signal()
nc = Signal()
- hit_set = Array(Signal() for i in range(TLB_NUM_WAYS))
- cache_valid_idx = Signal(INDEX_BITS)
+ hit_set = Array(Signal(name="hit_set_%d" % i) \
+ for i in range(TLB_NUM_WAYS))
+ cache_valid_idx = Signal(NUM_WAYS)
# Extract line, row and tag from request
comb += req_index.eq(get_index(r0.req.addr))
comb += req_row.eq(get_row(r0.req.addr))
comb += req_tag.eq(get_tag(ra))
+ if False: # display on comb is a bit... busy.
+ comb += Display("dcache_req addr:%x ra: %x idx: %x tag: %x row: %x",
+ r0.req.addr, ra, req_index, req_tag, req_row)
+
comb += go.eq(r0_valid & ~(r0.tlbie | r0.tlbld) & ~r1.ls_error)
- comb += cache_valid_idx.eq(cache_valid_bits[req_index])
+ comb += cache_valid_idx.eq(cache_valids[req_index])
m.submodules.dcache_pend = dc = DCachePendingHit(tlb_pte_way,
tlb_valid_way, tlb_hit_way,
# For a store, consider this a hit even if the row isn't
# valid since it will be by the time we perform the store.
# For a load, check the appropriate row valid bit.
- valid = r1.rows_valid[req_row % ROW_PER_LINE]
+ rrow = Signal(ROW_LINE_BITS)
+ comb += rrow.eq(req_row)
+ valid = r1.rows_valid[rrow]
comb += is_hit.eq(~r0.req.load | valid)
comb += hit_way.eq(replace_way)
# Whether to use forwarded data for a load or not
- comb += use_forward1_next.eq(0)
with m.If((get_row(r1.req.real_addr) == req_row) &
(r1.req.hit_way == hit_way)):
# Only need to consider r1.write_bram here, since if we
# cycles after the refill starts before we see the updated
# cache tag. In that case we don't use the bypass.)
comb += use_forward1_next.eq(r1.write_bram)
- comb += use_forward2_next.eq(0)
with m.If((r1.forward_row1 == req_row) & (r1.forward_way1 == hit_way)):
comb += use_forward2_next.eq(r1.forward_valid1)
with m.Else():
comb += opsel.eq(Cat(is_hit, nc, r0.req.load))
with m.Switch(opsel):
- with m.Case(0b101):
- comb += op.eq(Op.OP_LOAD_HIT)
- with m.Case(0b100):
- comb += op.eq(Op.OP_LOAD_MISS)
- with m.Case(0b110):
- comb += op.eq(Op.OP_LOAD_NC)
- with m.Case(0b001):
- comb += op.eq(Op.OP_STORE_HIT)
- with m.Case(0b000):
- comb += op.eq(Op.OP_STORE_MISS)
- with m.Case(0b010):
- comb += op.eq(Op.OP_STORE_MISS)
- with m.Case(0b011):
- comb += op.eq(Op.OP_BAD)
- with m.Case(0b111):
- comb += op.eq(Op.OP_BAD)
- with m.Default():
- comb += op.eq(Op.OP_NONE)
+ with m.Case(0b101): comb += op.eq(Op.OP_LOAD_HIT)
+ with m.Case(0b100): comb += op.eq(Op.OP_LOAD_MISS)
+ with m.Case(0b110): comb += op.eq(Op.OP_LOAD_NC)
+ with m.Case(0b001): comb += op.eq(Op.OP_STORE_HIT)
+ with m.Case(0b000): comb += op.eq(Op.OP_STORE_MISS)
+ with m.Case(0b010): comb += op.eq(Op.OP_STORE_MISS)
+ with m.Case(0b011): comb += op.eq(Op.OP_BAD)
+ with m.Case(0b111): comb += op.eq(Op.OP_BAD)
comb += req_op.eq(op)
comb += req_go.eq(go)
sync = m.d.sync
with m.If(r0_valid & r0.req.reserve):
-
# XXX generate alignment interrupt if address
# is not aligned XXX or if r0.req.nc = '1'
with m.If(r0.req.load):
comb += set_rsrv.eq(1) # load with reservation
with m.Else():
comb += clear_rsrv.eq(1) # store conditional
- with m.If(~reservation.valid | r0.req.addr[LINE_OFF_BITS:64]):
+ with m.If(~reservation.valid |
+ (r0.req.addr[LINE_OFF_BITS:64] != reservation.addr)):
comb += cancel_store.eq(1)
def reservation_reg(self, m, r0_valid, access_ok, set_rsrv, clear_rsrv,
wb_in = self.wb_in
for i in range(NUM_WAYS):
- do_read = Signal()
+ do_read = Signal(name="do_rd%d" % i)
rd_addr = Signal(ROW_BITS)
- do_write = Signal()
+ do_write = Signal(name="do_wr%d" % i)
wr_addr = Signal(ROW_BITS)
wr_data = Signal(WB_DATA_BITS)
wr_sel = Signal(ROW_SIZE)
wr_sel_m = Signal(ROW_SIZE)
- _d_out = Signal(WB_DATA_BITS)
+ _d_out = Signal(WB_DATA_BITS, name="dout_%d" % i)
way = CacheRam(ROW_BITS, WB_DATA_BITS, True)
setattr(m.submodules, "cacheram_%d" % i, way)
# Cache hit reads
comb += do_read.eq(1)
- comb += rd_addr.eq(early_req_row)
+ comb += rd_addr.eq(early_req_row[:ROW_BITS])
comb += cache_out[i].eq(_d_out)
# Write mux:
& wb_in.ack & (replace_way == i)):
comb += do_write.eq(1)
- # Mask write selects with do_write since BRAM
- # doesn't have a global write-enable
- with m.If(do_write):
- comb += wr_sel_m.eq(wr_sel)
+ # Mask write selects with do_write since BRAM
+ # doesn't have a global write-enable
+ with m.If(do_write):
+ comb += wr_sel_m.eq(wr_sel)
# Cache hit synchronous machine for the easy case.
# This handles load hits.
# All wishbone requests generation is done here.
# This machine operates at stage 1.
def dcache_slow(self, m, r1, use_forward1_next, use_forward2_next,
- cache_valid_bits, r0, replace_way,
+ cache_valids, r0, replace_way,
req_hit_way, req_same_tag,
- r0_valid, req_op, cache_tag, req_go, ra):
+ r0_valid, req_op, cache_tags, req_go, ra):
comb = m.d.comb
sync = m.d.sync
acks = Signal(3)
adjust_acks = Signal(3)
+ req_row = Signal(ROW_BITS)
+ req_idx = Signal(INDEX_BITS)
+ req_tag = Signal(TAG_BITS)
+ comb += req_idx.eq(get_index(req.real_addr))
+ comb += req_row.eq(get_row(req.real_addr))
+ comb += req_tag.eq(get_tag(req.real_addr))
+
sync += r1.use_forward1.eq(use_forward1_next)
sync += r1.forward_sel.eq(0)
for i in range(NUM_WAYS):
with m.If(i == replace_way):
ct = Signal(TAG_RAM_WIDTH)
- comb += ct.eq(cache_tag[r1.store_index])
+ comb += ct.eq(cache_tags[r1.store_index])
comb += ct.word_select(i, TAG_WIDTH).eq(r1.reload_tag)
- sync += cache_tag[r1.store_index].eq(ct)
+ sync += cache_tags[r1.store_index].eq(ct)
sync += r1.store_way.eq(replace_way)
sync += r1.write_tag.eq(0)
with m.Switch(r1.state):
with m.Case(State.IDLE):
- # XXX check 'left downto. probably means len(r1.wb.adr)
- # r1.wb.adr <= req.real_addr(
- # r1.wb.adr'left downto 0
- # );
- sync += r1.wb.adr.eq(req.real_addr)
+ sync += r1.real_adr.eq(req.real_addr)
sync += r1.wb.sel.eq(req.byte_sel)
sync += r1.wb.dat.eq(req.data)
sync += r1.dcbz.eq(req.dcbz)
# Keep track of our index and way
# for subsequent stores.
- sync += r1.store_index.eq(get_index(req.real_addr))
- sync += r1.store_row.eq(get_row(req.real_addr))
- sync += r1.end_row_ix.eq(
- get_row_of_line(get_row(req.real_addr))
- )
- sync += r1.reload_tag.eq(get_tag(req.real_addr))
+ sync += r1.store_index.eq(req_idx)
+ sync += r1.store_row.eq(req_row)
+ sync += r1.end_row_ix.eq(get_row_of_line(req_row))
+ sync += r1.reload_tag.eq(req_tag)
sync += r1.req.same_tag.eq(1)
with m.If(req.op == Op.OP_STORE_HIT):
pass
with m.Case(Op.OP_LOAD_MISS):
- #Display(f"cache miss real addr:" \
- # f"{req_real_addr}" \
- # f" idx:{get_index(req_real_addr)}" \
- # f" tag:{get_tag(req.real_addr)}")
- pass
+ sync += Display("cache miss real addr: %x " \
+ "idx: %x tag: %x",
+ req.real_addr, req_row, req_tag)
# Start the wishbone cycle
sync += r1.wb.we.eq(0)
# Clear stb and set ld_stbs_done
# so we can handle an eventual
# last ack on the same cycle.
- with m.If(is_last_row_addr(r1.wb.adr, r1.end_row_ix)):
+ with m.If(is_last_row_addr(r1.real_adr, r1.end_row_ix)):
sync += r1.wb.stb.eq(0)
comb += ld_stbs_done.eq(1)
# Calculate the next row address in the current cache line
- rarange = r1.wb.adr[ROW_OFF_BITS : LINE_OFF_BITS]
- sync += rarange.eq(rarange + 1)
+ row = Signal(LINE_OFF_BITS-ROW_OFF_BITS)
+ comb += row.eq(r1.real_adr[ROW_OFF_BITS:])
+ sync += r1.real_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq(row+1)
# Incoming acks processing
sync += r1.forward_valid1.eq(wb_in.ack)
with m.If(wb_in.ack):
- # XXX needs an Array bit-accessor here
- sync += r1.rows_valid[r1.store_row % ROW_PER_LINE].eq(1)
+ srow = Signal(ROW_LINE_BITS)
+ comb += srow.eq(r1.store_row)
+ sync += r1.rows_valid[srow].eq(1)
# If this is the data we were looking for,
# we can complete the request next cycle.
# Cache line is now valid
cv = Signal(INDEX_BITS)
- sync += cv.eq(cache_valid_bits[r1.store_index])
- sync += cv.bit_select(r1.store_way, 1).eq(1)
+ comb += cv.eq(cache_valids[r1.store_index])
+ comb += cv.bit_select(r1.store_way, 1).eq(1)
+ sync += cache_valids[r1.store_index].eq(cv)
sync += r1.state.eq(State.IDLE)
# Increment store row counter
# to be done which is in the same real page.
with m.If(req.valid):
ra = req.real_addr[0:SET_SIZE_BITS]
- sync += r1.wb.adr[0:SET_SIZE_BITS].eq(ra)
+ sync += r1.real_adr[0:SET_SIZE_BITS].eq(ra)
sync += r1.wb.dat.eq(req.data)
sync += r1.wb.sel.eq(req.byte_sel)
sync += log_out.eq(Cat(r1.state[:3], valid_ra, tlb_hit_way[:3],
stall_out, req_op[:3], d_out.valid, d_out.error,
r1.wb.cyc, r1.wb.stb, wb_in.ack, wb_in.stall,
- r1.wb.adr[3:6]))
+ r1.real_adr[3:6]))
def elaborate(self, platform):
# Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
cache_tags = CacheTagArray()
cache_tag_set = Signal(TAG_RAM_WIDTH)
- cache_valid_bits = CacheValidBitsArray()
+ cache_valids = CacheValidBitsArray()
# TODO attribute ram_style : string;
# TODO attribute ram_style of cache_tags : signal is "distributed";
comb += self.stall_out.eq(r0_stall)
# Wire up wishbone request latch out of stage 1
+ comb += r1.wb.adr.eq(r1.real_adr[ROW_OFF_BITS:]) # truncate LSBs
comb += self.wb_out.eq(r1.wb)
# call sub-functions putting everything together, using shared
self.maybe_tlb_plrus(m, r1, tlb_plru_victim)
self.cache_tag_read(m, r0_stall, req_index, cache_tag_set, cache_tags)
self.dcache_request(m, r0, ra, req_index, req_row, req_tag,
- r0_valid, r1, cache_valid_bits, replace_way,
+ r0_valid, r1, cache_valids, replace_way,
use_forward1_next, use_forward2_next,
req_hit_way, plru_victim, rc_ok, perm_attr,
valid_ra, perm_ok, access_ok, req_op, req_go,
req_hit_way, req_index, req_tag, access_ok,
tlb_hit, tlb_hit_way, tlb_req_index)
self.dcache_slow(m, r1, use_forward1_next, use_forward2_next,
- cache_valid_bits, r0, replace_way,
+ cache_valids, r0, replace_way,
req_hit_way, req_same_tag,
r0_valid, req_op, cache_tags, req_go, ra)
#self.dcache_log(m, r1, valid_ra, tlb_hit_way, stall_out)
yield dut.d_in.load.eq(1)
yield dut.d_in.nc.eq(nc)
yield dut.d_in.addr.eq(addr)
+ yield dut.d_in.byte_sel.eq(~0)
yield dut.d_in.valid.eq(1)
yield
yield dut.d_in.valid.eq(0)
+ yield dut.d_in.byte_sel.eq(0)
yield
while not (yield dut.d_out.valid):
yield
yield
+def dcache_random_sim(dut):
+
+ # start with stack of zeros
+ sim_mem = [0] * 512
+
+ # clear stuff
+ yield dut.d_in.valid.eq(0)
+ yield dut.d_in.load.eq(0)
+ yield dut.d_in.priv_mode.eq(1)
+ yield dut.d_in.nc.eq(0)
+ yield dut.d_in.addr.eq(0)
+ yield dut.d_in.data.eq(0)
+ yield dut.m_in.valid.eq(0)
+ yield dut.m_in.addr.eq(0)
+ yield dut.m_in.pte.eq(0)
+ # wait 4 * clk_period
+ yield
+ yield
+ yield
+ yield
+
+ print ()
+
+ for i in range(256):
+ addr = randint(0, 255)
+ data = randint(0, (1<<64)-1)
+ sim_mem[addr] = data
+ addr *= 8
+
+ print ("testing %x data %x" % (addr, data))
+
+ yield from dcache_load(dut, addr)
+ yield from dcache_store(dut, addr, data)
+
+ addr = randint(0, 255)
+ sim_data = sim_mem[addr]
+ addr *= 8
+
+ data = yield from dcache_load(dut, addr)
+ assert data == sim_data, \
+ "check %x data %x != %x" % (addr, data, sim_data)
+
+ for addr in range(256):
+ data = yield from dcache_load(dut, addr*8)
+ assert data == sim_mem[addr], \
+ "final check %x data %x != %x" % (addr*8, data, sim_mem[addr])
+
def dcache_sim(dut):
# clear stuff
yield dut.d_in.valid.eq(0)
yield
# Cacheable read of address 4
- data = yield from dcache_load(dut, 0x4)
+ data = yield from dcache_load(dut, 0x58)
+ addr = yield dut.d_in.addr
+ assert data == 0x0000001700000016, \
+ f"data @%x=%x expected 0x0000001700000016" % (addr, data)
+
+ # Cacheable read of address 20
+ data = yield from dcache_load(dut, 0x20)
addr = yield dut.d_in.addr
- assert data == 0x0000000100000000, \
- f"data @%x=%x expected 0x0000000100000000" % (addr, data)
+ assert data == 0x0000000900000008, \
+ f"data @%x=%x expected 0x0000000900000008" % (addr, data)
# Cacheable read of address 30
- data = yield from dcache_load(dut, 0x30)
+ data = yield from dcache_load(dut, 0x530)
addr = yield dut.d_in.addr
- assert data == 0x0000000D0000000C, \
- f"data @%x=%x expected 0000000D0000000C" % (addr, data)
+ assert data == 0x0000014D0000014C, \
+ f"data @%x=%x expected 0000014D0000014C" % (addr, data)
# 2nd Cacheable read of address 30
- data = yield from dcache_load(dut, 0x30)
+ data = yield from dcache_load(dut, 0x530)
addr = yield dut.d_in.addr
- assert data == 0x0000000D0000000C, \
- f"data @%x=%x expected 0000000D0000000C" % (addr, data)
+ assert data == 0x0000014D0000014C, \
+ f"data @%x=%x expected 0000014D0000014C" % (addr, data)
# Non-cacheable read of address 100
data = yield from dcache_load(dut, 0x100, nc=1)
assert data == 0x0000004100000040, \
f"data @%x=%x expected 0000004100000040" % (addr, data)
- # Store at address 30
- yield from dcache_store(dut, 0x30, 0x121)
+ # Store at address 530
+ yield from dcache_store(dut, 0x530, 0x121)
# Store at address 30
- yield from dcache_store(dut, 0x30, 0x12345678)
+ yield from dcache_store(dut, 0x530, 0x12345678)
- # 3nd Cacheable read of address 30
- data = yield from dcache_load(dut, 0x30)
+ # 3nd Cacheable read of address 530
+ data = yield from dcache_load(dut, 0x530)
addr = yield dut.d_in.addr
assert data == 0x12345678, \
f"data @%x=%x expected 0x12345678" % (addr, data)
+ # 4th Cacheable read of address 20
+ data = yield from dcache_load(dut, 0x20)
+ addr = yield dut.d_in.addr
+ assert data == 0x0000000900000008, \
+ f"data @%x=%x expected 0x0000000900000008" % (addr, data)
+
yield
yield
yield
yield
-def test_dcache():
+def test_dcache(mem, test_fn, test_name):
dut = DCache()
- vl = rtlil.convert(dut, ports=[])
- with open("test_dcache.il", "w") as f:
- f.write(vl)
- mem = []
- for i in range(0,128):
- mem.append((i*2)| ((i*2+1)<<32))
- memory = Memory(width=64, depth=16*8, init=mem)
+ memory = Memory(width=64, depth=16*64, init=mem)
sram = SRAM(memory=memory, granularity=8)
m = Module()
m.d.comb += sram.bus.stb.eq(dut.wb_out.stb)
m.d.comb += sram.bus.we.eq(dut.wb_out.we)
m.d.comb += sram.bus.sel.eq(dut.wb_out.sel)
- m.d.comb += sram.bus.adr.eq(dut.wb_out.adr[3:])
+ m.d.comb += sram.bus.adr.eq(dut.wb_out.adr)
m.d.comb += sram.bus.dat_w.eq(dut.wb_out.dat)
m.d.comb += dut.wb_in.ack.eq(sram.bus.ack)
sim = Simulator(m)
sim.add_clock(1e-6)
- sim.add_sync_process(wrap(dcache_sim(dut)))
- with sim.write_vcd('test_dcache.vcd'):
+ sim.add_sync_process(wrap(test_fn(dut)))
+ with sim.write_vcd('test_dcache%s.vcd' % test_name):
sim.run()
if __name__ == '__main__':
- test_dcache()
+ dut = DCache()
+ vl = rtlil.convert(dut, ports=[])
+ with open("test_dcache.il", "w") as f:
+ f.write(vl)
+
+ mem = []
+ for i in range(0,512):
+ mem.append((i*2)| ((i*2+1)<<32))
+
+ test_dcache(mem, dcache_sim, "")
+ test_dcache(None, dcache_random_sim, "random")
projects / soc.git / blobdiff