"""
-from nmigen.compat.sim import run_simulation
+from nmigen.compat.sim import run_simulation, Settle
from nmigen.cli import verilog, rtlil
from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
from nmutil.iocontrol import RecordObject
self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf
self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit
-# TODO:
+# TODO: elaborate function
class DualPortSplitter(Elaboratable):
once that is done each pair of ports may be wired directly
to the dual ports of L0CacheBuffer
+
+ The split is carried out so that, regardless of alignment or
+ mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
+ of the address, whilst outgoing PortInterface[1] takes
+ bit 4 == 1.
+
+ PortInterface *may* need to be changed so that the length is
+ a binary number (accepting values 1-16).
"""
- pass
+ def __init__(self):
+ self.outp = []
+ self.outp[0] = PortInterface(name="outp_0")
+ self.outp[1] = PortInterface(name="outp_1")
+ self.inp = PortInterface(name="inp")
+
+ def elaborate(self, platform):
+ splitter = LDSTSplitter(64, 48, 4)
class DataMergerRecord(Record):
def data_merger_merge(dut):
print("data_merger")
#starting with all inputs zero
+ yield Settle()
en = yield dut.data_o.en
data = yield dut.data_o.data
assert en == 0, "en must be zero"
assert data == 0, "data must be zero"
yield
+
yield dut.addr_array_i[0].eq(0xFF)
for j in range(dut.array_size):
yield dut.data_i[j].en.eq(1 << j)
yield dut.data_i[j].data.eq(0xFF << (16*j))
- yield
+ yield Settle()
+
en = yield dut.data_o.en
data = yield dut.data_o.data
assert data == 0xff00ff00ff00ff00ff00ff00ff00ff
def test_l0_cache():
dut = TstL0CacheBuffer()
- vl = rtlil.convert(dut, ports=dut.ports())
- with open("test_basic_l0_cache.il", "w") as f:
- f.write(vl)
+ #vl = rtlil.convert(dut, ports=dut.ports())
+ #with open("test_basic_l0_cache.il", "w") as f:
+ # f.write(vl)
run_simulation(dut, l0_cache_ldst(dut),
vcd_name='test_l0_cache_basic.vcd')